Diksha Sharma

CEO

Pune, Maharashtra, India6 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL performance analysis and system-level modeling.
  • Proficient in automating performance analysis workflows.
  • Strong background in memory subsystem performance evaluation.
Stackforce AI infers this person is a Semiconductor Engineer specializing in performance analysis and system modeling.

Contact

LinkedIn

Skills

Core Skills

Performance AnalysisSystem-level ModelingPerformance ModelingAutomation

Other Skills

ModelingMemory subsystemsDDR5LPDDR5LatencyBandwidthThroughputAnalysisPerformance modelsRTL behaviorArchitectural trade-offsPythonPerlAutomation scriptsDDR SDRAM

About

Semiconductor engineer focused on RTL performance analysis and system-level modeling in semiconductor designs. Experienced in developing performance models, analyzing throughput and latency metrics, and identifying architectural bottlenecks in complex SoC systems. Strong interest in computer architecture, system simulation, and performance optimization.

Experience

6 yrs 9 mos
Total Experience
3 yrs 4 mos
Average Tenure
4 yrs 11 mos
Current Experience

Cadence

3 roles

Lead Design Engineer

Promoted

Jan 2026 – Present · 5 mos

  • Performed performance analysis and modeling for memory subsystems including DDR5 and LPDDR5
  • Built system-level models to evaluate latency, bandwidth, and throughput for memory interfaces
  • Identified performance bottlenecks in memory controller and interconnect paths
  • Currently contributing to performance modeling and analysis for LPDDR6 architecture
Performance analysisModelingMemory subsystemsDDR5LPDDR5Latency+3

Design Engineer II

Promoted

Jul 2022 – Dec 2025 · 3 yrs 5 mos

  • Developed performance models to analyze RTL behavior and evaluate architectural trade-offs
  • Developed Python and Perl automation scripts to streamline RTL performance analysis workflows
  • Automated data extraction, log analysis, and report generation for simulation results
Performance modelsRTL behaviorArchitectural trade-offsPythonPerlAutomation scripts+2

Software Engineer 1

May 2021 – Jun 2022 · 1 yr 1 mo

DDR SDRAM

Gs lab

2 roles

Software Developer

Jul 2019 – May 2021 · 1 yr 10 mos · Pune Area, India

Software Engineer Intern

Oct 2018 – Jun 2019 · 8 mos · Pune Area, India

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Software systems

Jul 2025 – Jun 2027

Lovely Professional University

Bachelor of Technology — Computer Science

Jan 2015 – Jan 2019

Jawahar Navodaya Vidyalaya ,Shajapur

Higher Secondary Education — Science Stream

Jan 2007 – Jan 2014

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