Diwakar Mohan

Senior Software Engineer

Hyderabad, Telangana, India14 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Android Development and Machine Learning.
Proven track record in IC design and simulation.
Recognized for leadership and mentoring in engineering teams.

Stackforce AI infers this person is a Software Development Engineer specializing in Android and IC design.

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Skills

Core Skills

Android DevelopmentMachine LearningIc DesignC++

Other Skills

Azure Distributed ServicesAndroid JetpackCadence Virtuoso® ToolParasitic ExtractionSimulationPythonUnixSoftware DesignSolution ArchitectureAndroid FrameworkAndroid DesignEDAAlgorithmsSoftware EngineeringC (Programming Language)

About

Experienced Senior Software Engineer with a demonstrated history of working in the computer software industry. Skilled in C++, Data Structures, Object Oriented Designs, Android Development (Frontend/Backend), Azure Services and EDA. Knowledge of Machine Learning and Artificial Neural Networks. Strong engineering professional with a Bachelor of Technology - BTech focused in Electrical Engineering from Indian Institute of Technology (IIT), Varanasi. - C++/C - Data Structures & Algorithms - STL - Machine Learning/Artificial Neural Networks (Certification Course) - Python, NumPy, TensorFlow, Pandas - Android Development - Android Autofill Framework - Azure Distributed Services - Cadence Virtuoso® Tool for designing full-custom integrated circuits and simulation - Cadence Virtuoso® Schematic & Layout Design/Editor - Multi Fabric Parasitic Extraction (Board-Package-Chip) & Back Annotation - RF System Design Flow - PCB Packaging - IC Design & Simulation - Verilog/VHDL Import - MFC - Multi-threaded Processing - Microsoft DirectShow, Windows COM, Microsoft Active X, FFMpeg

Experience

14 yrs 5 mos

Total Experience

10 yrs 11 mos

Average Tenure

14 yrs 5 mos

Current Experience

Microsoft

Senior Software Engineer

Jan 2019 – Present · 7 yrs 5 mos · Hyderabad, Telangana, India

Android Development; Android Autofill Framework; Java; Kotlin; Dependency Injection; Android Test Framework; Machine Learning; Azure Distributed Services; C++
GroupMe
Engineering initiatives, mentoring team members to adopt Android Architectural best practices and Test Framework to improve on application quality and reliability.
Microsoft Authenticator
Building and shipping Autofill solution for user’s personal information using Intelligence Library and Azure Distributed Services.
Providing Autofill capability in Microsoft’s flagship device (Microsoft Surface Duo).
Mentoring new team members helping them to onboard to our product.
Product security initiatives and process improvements (Security and Customer Champ)
Autofill Intelligence Library
Architected the Intelligence Library, which is a backbone for Autofill solution.
Collaboration with partner Apps to help them onboard to Intelligence Library.
Org-wide tech talks on the design of our product’s Autofill solution.

Android DevelopmentMachine LearningAzure Distributed ServicesC++

Cadence design systems

2 roles

Principal Software Engineer

Jan 2016 – Present · 10 yrs 5 mos

Multi Fabric Parasitic Extraction and Simulation:
Designed, developed & productized the entire flow for creating the extracted design with parasitic models (s-parameter) to enable the user to carry out parasitic aware system level simulation of IC and PCB.
Assumed the ownership, leadership role, problem solving, decision making and product roadmap by leading an engineering team.
Improved the simulation time of real world package designs by supporting the hierarchical package designs.
Enabled the plugin-based solution to enhance the user experience.
One of the first products from my group which started generating revenue by early customer adoption.
Technologies:
C++, IC Design; Cadence Virtuoso® Tool, Virtuoso® Schematic & Layout, IC Design & Simulation, Allegro Sip Layout, Parasitic Extraction, Board Packaging, RF System Design Flow
Other Leadership roles:
Managed an engineering team for other multiple projects (Device Mapping, Multi Fabric [Board-Package-Chip] Extraction and Simulation).
Other Projects:
Optimized Circuit Simulation using Machine Learning:
Developed algorithm and computer program for automatically reducing the number of parametric sweeps and corner simulation required to fine tune device parameter values in an electronic circuit design.
Technologies:
Python; Unix
Recognition/Awards:
Catalyst Award
Team Player Award
Take a Bow Award
Electronic Products’ Product of the Year award globally.
Product showcased to customers at International Microwave Symposium (IMS) at Boston, MA.

C++IC DesignCadence Virtuoso® ToolParasitic Extraction

Senior Member Of Technical Staff

Jan 2012 – Present · 14 yrs 5 mos

Virtuoso® System Design Platform (Product of the Year):
Improved performance of Verilog/VHDL text import by redesigning a generic C++ architectural design. Symbol creation space optimization for huge pins by distributing the pins on all sides of the symbol.
Enabled schematic PCB binding to seamlessly bind two schematic designs primarily for board and package designs. Enabled the simulation of the circuit design by creating the Test Bench Design for the package designs.
Optimized the user viewing experience by creating the text displays and markers in the schematic editor.
Technologies:
C++; IC Design; Cadence Virtuoso® Tool, Virtuoso® Schematic & Layout, IC Design & Simulation, Allegro Sip Layout, Parasitic Extraction, Board Packaging
Recognition:
C++ Skills Challenge Award (Top 2% of total Cadence Design Systems employees)
Recognition for Machine Learning Hackathon
Submitted Patent applications for research work