Jan 2022 – Sep 2024 · 2 yrs 8 mos

Jun 2019 – Dec 2021 · 2 yrs 6 mos

Apr 2018 – Jun 2019 · 1 yr 2 mos

Apr 2016 – Mar 2018 · 1 yr 11 mos

Feb 2015 – Mar 2016 · 1 yr 1 mo

Apr 2010 – Jan 2015 · 4 yrs 9 mos

• Developed test programs for the TI's high volume DSP's, PMIC's,DRIVERS and interfaces on ATE (VLCT)
• Characterized HSI modules USB2,USB3,HDMI,DSI and MPHY for all PVT corners.
• Developed schematic and did simulations for multisite solutions.
• Multi-probe(Wafer Sort) and Final Test production test development and deployment at ATE Sites.
• Proficient with lab instruments like oscilloscopes, logic analyzers, thermal streams.
• Done test program conversion for the legacy testers- Dual controller to single controller VLCT, IMPACT to VLCT.
• Data analysis Cp,Cpk and GRR reports.
• Yield analysis and improvement through TTR and with different test methodology.
• Test data analysis for Gauge Repeatability and Reproducibility. Data collection and statistical analysis using Testware, PCW.
• Good in debug activities related to the test solution at all levels; Si-Debug, Board Troubleshooting, Test Implementation.
• Mentored 5 member team for the Silicon Test Development activity.

Apr 2009 – Mar 2010 · 11 mos

• Responsible for the hardware design of the experiments board.
• Training the team regarding the micro-controller concepts and Interface.
• Developed the ADC interface code for MSP430F2013 and MSP430FG4618 to measure the temperature using internal temperature sensor and ADC
• Done the SPI interface between MSP430FG4618 and MSP430F2013 on Texas Instruments analog lab in Box.
• Developed application for DC motor control with MSP430F2274

Jan 2007 – Mar 2009 · 2 yrs 2 mos · Bangalore

• Developed the DVB-T receiver Software model on VLIW architecture.
• Done DVB-T receiver fixed point analysis.
• Developed “C” and Assembly code for the Bit De-inter leaver and De randomizer.
• Developed Fixed point algorithm in 'C' language for the Frame Synchronization and
• Fine synchronization. Interfaced implemented 'C' algorithms with MATLAB.
• Acted as key member to get Instruction set architecture for Universal Demodulator.
• Acted as the communication channel between the Algorithm team and RTL design team.
• Used and verified the simulator and assembler developed as the reference model to verify the software development.
• Implemented “FAST division algorithm” in C .
• Design of Simplified soft decision De-mapper for DVB-T (MATLAB - Floating point model and software model).
• Tested software model for all standard channel specifications.
• Tested and qualified software model for real time captured test streams from DTVLabs on FPGA prototype of Custom VLIW processor.

Jul 2006 – Dec 2006 · 5 mos · Manipal

• •Basic Circuit analysis, CMOS VLSI Design and layout ,CMOS process & analog design and layout.