Girish Awasthi — Product Manager

I am Girish Awasthi working as a Digital Design Engineer Consultant at NXP Semiconductors, in the FDIP SRAM & ROM e-Memory Design team in Bangalore . My focus lies in functional verification, custom design formal verification, and compiler development, contributing to next-generation semiconductor memory solutions across 16 nm, 22 nm, 28 nm, and 40 nm nodes. At NXP Semiconductors, I have: • Led project responsibilities for memory compilers at multiple technology nodes. • Verified SRAM models in Verilog with emphasis on performance & reliability. • Built a common verification testbench for multiple tech nodes, streamlining workflows. • Optimized code coverage using Cadence IMC and performed FSM hangup verification with Synopsys ESPCV. • Authored test plans, corruption strategies, and compiler checklists to strengthen clarity and cross-team communication. • Mentored junior engineers in verification methodologies and best practices. Previous Experience & Research As a Research Intern at IIT Patna, I explored memristor-based circuit design, successfully building a low-pass filter with improved bandwidth and lower power dissipation, combining both theoretical and practical innovation. Technical Toolbox • Languages: Verilog, SystemVerilog • EDA Tools: Cadence Xcelium, Cadence SimVision, Cadence IMC, Synopsys ESPCV, Xilinx ISE, LTSpice • Platforms: Windows & Linux Open to connect with professionals in semiconductor design, digital verification, VLSI R&D. Always eager to share knowledge, learn, and explore new opportunities.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on digital verification and memory solutions.

Location: Bengaluru, Karnataka, India

Experience: 2 yrs 10 mos