Sep 2019 – Dec 2023 · 4 yrs 3 mos · Bengaluru Area, India · On-site

• Post silicon Bring up, validation and Debug lead
• As Post silicon lead for Snapdragon Gen 1+, was responsible for silicon bring up, debug of critical issues and successful commercialization of the silicon. Work with various partner teams like Design, DV, DFT, PD, SW, Chipset, PTE, PDT, SLT teams to ensure smooth CS (Customer Sample) delivery.
• Was post silicon and Sysdebug lead for Snapdragon X Elite chip. Snapdraon X Elite was a premium offering from Qualcomm for laptops which garnered wide industry attention due to a brand new CPU architecture (https://www.qualcomm.com/products/mobile/snapdragon/pcs-and-tablets/snapdragon-x-elite). As a lead was responsible in driving validation team, work closely with partner teams to rootcause and find workarounds for issues seen in pre-sil, thus unblocking tapeouts, and in post-sil, enabling successful product launch.
• Silicon Debug lead for many Snapdragon 7/6/4 series of silicon. My role was to work in close collaboration with SLT / PTE/ Silicon Design / SW teams in finding a root cause for issues found in production. Come up with a strategy to screen any marginal defects or provide workarounds to customer to enable successful customer launches.
• My role had direct impact on successful customer launches and was crucial in successful enablement of Snapdragon product on customer platforms. Received many accolades for root cause of critical customer failures and also successful commercialization of multiple generations of Chips.

Mar 2018 – Sep 2019 · 1 yr 6 mos · Bengaluru Area, India

• Firmware lead for SanDisk retail class of products working on SSD firmware
• SanDisk developed a core in-house for the first time based on RISC-V ISA. I was responsible to develop PSP (Processor Support Package) for RISC-V core and also port firmware to RISC-V architecture.
• Lead a team to measure and compare KPIs with the existing core and identify bottlenecks. Analyze and submit report on code density and core performance along with recommendations on improvement area. Presented code density study at RISC-V workshkp conducted at IIT-M.
• Well versed with building toolchains

Jan 2012 – Mar 2018 · 6 yrs 2 mos · Bengaluru, Karnataka, India

• Have extensively worked on software development for Baseboard Management Controller (BMC) for server boards.
• Responsibilities:
• Responsible to explore and work with ASIC team in developing HW modules that can seamlessly interface with the Software and provide better performance. Get involved with ASIC team right from RTL verification and also FPGA validations. And post tapeout, gets involved in bringing up the ASIC and verify/validate the modules. Responsible to deliver the complete package of ‘U-Boot + Linux’ along with drivers as SDK(BSP), to the customers, which they can use to develop their own software.
• Responsibilities include,
• ARM Initialization (A9 and CM3)
• Develop drivers for SPI flash devices, I2C, eSPI, LPC, PWM Fantach
• Linux Kernel Device Tree
• u-boot porting for ARM SOC
• Crypto and secure boot
• Leading the Test Automation initiative using Python/Perl scripting
• hands on experience in building and maintaining ARM tool chain(using crosstool-ng) for different flavors of ARM processors needed for our SOC
• Worked on a POC to come up with a virtual HBA driver which will allow any system on the network to mount the storage exposed by BMC
• Familiar with debugging using ARM DS-5 debugger
• Automate the release process of the BSP
• git CI/CD

Jan 2012 – Dec 2016 · 4 yrs 11 mos

• Joined Emulex in January 2012 as Senior Engineer. Emulex got acquired by Avago and later became Broadcom. Pilot product line got acquired from Broadcom by 'Aspeed Technologies' in 2016. Hence moved to Aspeed on Dec 2016.

Sep 2005 – Jan 2012 · 6 yrs 4 mos · Bengaluru, Karnataka, India

• Client: NetApp (Erstwhile LSI)
• Volume Configuration for RAID Controller FW:
• Part of a team that develops features related to config aspects of a Storage Array.
• Designed and developed a feature called ‘Expandable Repository Volumes’ that makes RAID volume expansion faster.
• Was involved in developing ‘Thin Provisioning’ feature for LSI arrays
• Was part of the team to develop “Volume Migration” feature for the storage arrays. This is about importing/exporting volumes from/to different Storage Arrays.
• Played an important role in developing a feature called “Secure Volumes” that uses FDE drives manufactured by Seagate.
• Was a key resource for Volume Config features that were implemented from India
• IO Services Project:
• Developed a feature to introduce IP support for inter-controller communication. Traditionally the controllers were using backend drive channels to talk to each other (using SCSI). Support was added to make the Inter-controller communication happen via an internal NIC (using TCP/IP).
• The challenge was to establish an infrastructure for IP communication between controllers without disturbing the existing components hierarchy. Worked closely with the architects since this involved a lot of architectural analysis and design.
• Adding new RPC calls to perform volume configurations
• SFCB:
• Develop a Management Interface called Embedded SMIS agent which was to port SFCB from Linux to VxWorks
• Performance of OSA Infrastructure (Xen Hypervisor):
• Was entrusted with a responsibility to analyze/benchmark the performance of RAID FW stack running on Xen Hypervisor.
• Technical works/Internal Projects:
• Out of personal interest did a project – ‘Unattended Disk Management’ for an event called Osmosis(MindTree’s Tech Fest). Successfully demonstrated & won the best project award for that year