JASVARDHAN REDDY

Software Engineer

Bengaluru, Karnataka, India15 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Proven expertise in RTL design and SoC integration.
Led critical design projects in semiconductor industry.
Strong background in FPGA design for telecommunications.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong RTL and FPGA design capabilities.

Contact

Skills

Core Skills

Rtl DesignSocFpga DesignVerification

Other Skills

DebuggingMicro-architecture documentationPre-silicon validationPost-silicon validationVerilogSDH protocolsTestingSimulationsVHDLEmbedded SystemsR&DElectronicsAlgorithmsProgrammingCircuit Design

About

I'm an enthusiastic team player, enjoy working with people. My current and past companies recognized my skills to accommodate to the org needs. I intend to be the part of main driving force for the company and do innovative work while accepting challenging tasks and prove myself an asset.

Experience

15 yrs 10 mos

Total Experience

5 yrs 3 mos

Average Tenure

8 yrs 6 mos

Current Experience

Qualcomm

3 roles

Senior Staff Engineer/Manager

Dec 2023 – Present · 2 yrs 6 mos

Staff Engineer/ Manager

Dec 2020 – Dec 2023 · 3 yrs

Senior Lead Engineer

Dec 2017 – Dec 2020 · 3 yrs

Intel corporation

Component Design Engineer

Jan 2012 – Dec 2017 · 5 yrs 11 mos · Bengaluru Area, India

Currently working as a Subsytem RTL integration lead for a one of the critical blocks in SoC.
In the past, I worked as Designer for DRAM controller, worked on DDR3 and LPDDR4 protocol. Also designer for Pin-Mux logic and integration of above blocks along with all IO pads at SoC.
Worked on RTL Design for debug blocks.
Designed configurable PCM block.
PoC of configurable I2S using the ALTERA NIOS FPGA eco-system.
Work includes working with the pre-silicon validation team as well as post – silicon validation team and debugging them.
Responsible for design issues with the backend teams and also the software teams.
Responsible for the micro-architecture documentation of the design blocks.
Lead the design workgroup with Architects & Leads to identify solutions for roadblocks.
Coded validation assertions/ review code coverage to enable the validation team speed up verification for a block.

RTL DesignDebuggingSoCMicro-architecture documentationPre-silicon validationPost-silicon validation

Tejas networks

R & D engineer

Jul 2010 – Dec 2011 · 1 yr 5 mos · Banaglore

FPGA Designer for Optical Networking Equipment involving SDH protocols.
Complete product cycle from concept to field testing involving FPGA design, testing and its verification.
Developing design specifications.
Interacting with firmware and software development teams to determine the hardware interface.
Developing FPGA design architectures and coding in Verilog.
Generating internal and customer documentation.
Validating FPGA and hardware designs in cooperation with Firmware & Software engineers to ensure that designs are reliable.
Design support for field issues at System-level.

FPGA DesignVerilogSDH protocolsTestingVerification