J

Jayesh Salve

CEO

Navi Mumbai, Maharashtra, India0 mo experience

Key Highlights

  • Proficient in Universal Verification Methodology (UVM) and SystemVerilog.
  • Strong interpersonal communication and teamwork skills.
  • Currently pursuing a Master's in VLSI & Embedded Systems.
Stackforce AI infers this person is a VLSI and Embedded Systems Engineer.

Contact

LinkedIn

Skills

Other Skills

Universal Verification Methodology (UVM)SystemVerilogInterpersonal CommunicationTime EfficiencyTeamworkAdaptationVerilog

Education

JSPM BHIVRABAI SAWANT INSTITUTE OF TECHNOLOGY AND RESEARCH

Master's in Engineering — VLSI & Embedded Systems

Oct 2022 – Jun 2024

Mumbai University Mumbai

Bachelor of Technology - BTech

Jan 2014 – Jan 2020

Stackforce found 100+ more professionals with Universal Verification Methodology (UVM) & SystemVerilog

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