Jaypal Rathod

DevOps Engineer

Mumbai, Maharashtra, India3 yrs experience

Highly Stable

Key Highlights

Expert in CXL and PCIe protocol verification.
Strong background in SoC design and RTL integration.
Proficient in multiple verification tools and methodologies.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in protocol verification and SoC design.

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Skills

Core Skills

Ip VerificationProtocol VerificationQuality AssuranceSoc DesignRtl Integration

Other Skills

UDIMMSystem verilogCXLPCIeRegression AnalysisDebuggingCheetah EnvSpyglass LintDDRProtocol AnalyzerSpyglass CDCUniversal Verification Methodology (UVM)PCIe protocolCXL ProtocolLinux

About

Presently working as Senior Verification engineer for CXL, PCIE, DDR, UDIMM, RDIMM, DFI VIP at Synopsys Inc in VIP Team Worked as SOC Design Engineer in Xeon and Networking Engineering Team for six months at Intel India. Have thorough understanding of RTL Connectivity & Integration. Strong quality assurance professional with a Master's degree focused in VLSI Design from NIT Surathkal, Karnataka & Strong engineering professional with a B.Tech focused in Electrical engineering from Veermata Jijabai Technological Institute (VJTI), Mumbai. Skills : HDL language: Verilog, System Verilog and basics of UVM Protocol knowledge: PCIe (till Gen6.0), CXL( till gen 3.0), DDR5 Basics, LPIF Spec, IDE Spec, Programming Languages: C++, Python Operating systems: Linux, Git Tools & Technologies: Spyglass CDC, Mentor Graphics Modelsim and Questa Sim , Xilinx vivado simulator, Cadence Virtuoso, Tanner EDA, LTSpice, NGSpice, Logisim, Magic.

Experience

3 yrs

Total Experience

3 yrs

Average Tenure

3 yrs

Current Experience

Synopsys inc

2 roles

Staff Protocol Solution Engineer

May 2026 – Present · 1 mo · Hyderabad, Telangana, India · Hybrid

UDIMMSystem verilogIP VerificationProtocol Verification

Senior Protocol Solution Engineer

Jun 2023 – Present · 3 yrs · Hyderabad, Telangana, India · Hybrid

Working in IP Verification Team (VIP) which focuses on the development, Integration & providing solutions related to VIP’s & Test Suite. Verification Engineer for PCIe and CXL,DDR, UDIMM, RDIMM, DFI protocol specific Designs.
1. Daily regression analysis for CXL using simulation and emulator tools.
2.Debugging the failed testcases and finding root cause of failure testcase.
3. knowledge of PCIE Gen1/Gen2/Gen3/Gen4/Gen5/ Gen6 protocols.
4. Working on High speed interconnect CXL1.0/CXL1.1/CXL2.0/CXL3.0 IP Level verification.
5. Creating testcases and bring up those features into regression.
6. Finding bugs and improve quality of IP as per the specifications.
7. Knowledge on cache Coherence protocol
(MESI states) and CXL.mem.
8. Knowledge of DDR, UDIMM, RDIMM Spec with VIP working experience.

Cheetah EnvSpyglass LintSoC DesignRTL Integration

Intel corporation

Graduate Technical Intern

Nov 2022 – May 2023 · 6 mos · Bengaluru, Karnataka, India

SoC Design Engineer
Worked in Xeon and Networking Engineering Team which focuses on the development and
integration of XEON processor.
Worked on RTL connectivity & integration for SOC. Learned tools like VCS, Spyglass Lint, Spyglass
CDC, and Intel’s Cheetah Env.

The brihanmumbai electric supply & transport undertaking ( best)

Engineer Intern

Dec 2017 – Jan 2018 · 1 mo · Mumbai Metropolitan Region

undergone training in power distribution system and explored various sections like O&M, Testing, Distribution workshop, Control Room, Street Light Construction and Maintenance department, Erection
department ,Network Planning etc.

Indian railways

Summer Intern

Nov 2017 – Dec 2017 · 1 mo · Mumbai, Maharashtra, India

I understood power distribution system and explored various sections like pantograph, Brake, auxiliary warning system, Testing, workshop, Control Room, Learn about working of various parts of EMU and EMU scheduling, overhauling and maintenance etc.