Jobin James

Software Engineer

Bengaluru, Karnataka, India16 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

12+ years of software development experience in C++.
Expert in multi-threaded and multi-process architecture.
Strong background in EDA and design industry.

Stackforce AI infers this person is a Backend-heavy Fullstack engineer in the EDA/Design industry.

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Skills

Core Skills

MultithreadingC++Algorithm DesignFpga Prototyping

Other Skills

ASICAlgorithmsArchitectureCComputer ArchitectureCore JavaDFTData StructuresDebuggingDesign PatternsEmbedded SystemsHibernateLeadershipLinuxMatlab

About

1. 12+ yrs of total work experience on Software development using C++. MTech from IIT Delhi on computer architecture and VLSI CAD. 11 years in EDA/Design industry. 2. Delivered multiple high performance complex features across multiple products, based on multi-threaded and multi-process architecture. Contributed in both individual and lead role. 3. Exposure to entire SDLC by working in small teams(requirement analysis, class diagram/UML/Design pattern, algorithm development, unit test cases, TDD) 4. Team player. Actively involved in mentoring , hiring, architecture design and technology consultance. 5. Strong knowledge of back end compiler optimizations, graph theory and parallel programming/mutli threading. 6. Working knowledge of machine learning frameworks like torch, tensorflow and scikit. Used linear regression and Decision tree for Placement correlation analysis.

Experience

16 yrs 5 mos

Total Experience

3 yrs 3 mos

Average Tenure

5 yrs

Current Experience

Synopsys inc

2 roles

Principal Engineer

Promoted

Feb 2024 – Present · 2 yrs 4 mos

Staff Engineer

May 2021 – Jan 2024 · 2 yrs 8 mos

Working on multi-threaded C++ development for prototyping and emulation products, resulting in 2X improvement over existing flow.
Mentored team members on multiple aspects of flow. Specializing in Global optimizations, gated clock conversion, DPI(encryption support), clock reporting. Deep experience of synthesis and optimization techniques for FPGAs as well as ASICs.
Mentored multiple junior engineers and colleagues to help them get up to speed on code and flow. Involved in hiring activities for team.
Preparing requirement and implementation spec for making existing features in tool multi threaded. Implemented few features and guiding junior engineers on certain taks.
Assisting management with overall performance and QOR planning for enhancing the tool and planning release to customers.

LeadershipArchitectureFPGA prototypingLinuxData StructuresMultithreading+2

Adobe

Computer Scientist 2

Apr 2020 – May 2021 · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

Design and development of APIs for UI.
Architecture and implementation of multiple aspects like selector engine, theming support etc.
Mentoring junior engineers and code review. API framework architecure discussion and review. Participated in hiring events to grow the team.
Supported multiple products like Photoshop, AI, XD on both Windows and Mac.
Advanced multi-threaded development in C++ for cutting edge performance.

Synopsys inc

Senior R&D 2

Feb 2017 – Mar 2020 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Development of RTL compiler and mapping for FPGA, using C++

Algorithm DesignFPGA prototypingLinuxC++

Nvidia

4 roles

Senior Developer

Promoted

Mar 2015 – Feb 2017 · 1 yr 11 mos

CAD tools for DFT Scan Insertion.
Mapping DFT CAD problem to Graph Algorithms (e.g., Maximum bipartite matching), and solving/coding them optimally
Understanding of requirement, adding new features in C++ based tool, writing unit test cases and fixing bugs.
Mentoring junior engineers and Interns
Complete ownership of DFT analysis flow, and other blocks in DFT flow
Using good software designs to improve the flow, and make it modular.

Linux

Software Developer

Jul 2013 – Feb 2015 · 1 yr 7 mos

Tool development for Architecture group
Develop C++ based performance models for Memory Controller of Nvidia's Tegra Processor.
Involved in High Level Design and Implementation
Adding new features to performance simulator and validation of the model.
Writing tests to verify/validate the model using perl/python/shell scripts for automation of the various steps involved in validation/verification.
Complete ownership of Response X-Bar, Arbiters in Simulator, and its correlation with RTL

Linux

Intern

Jan 2013 – Jun 2013 · 5 mos

Developing interface accurate C++ model for UFS-HC.
Tool was used by used by driver team while hardware development was still in progress.
Verification team also used our C++ models, for comparison the o/p of the DUT(Device under test) with our model.

Linux

IIT Delhi, Graduate Student

Jul 2011 – Jun 2013 · 1 yr 11 mos

This course was sponsored by Nvidia. Course work involved Algorithms,and applications to Hardware modelling/synthesis. As a part of the thesis work, I did modelling of UFS-HC at Nvidia.
Did elective courses on Image processing and Operating systems

Linux

Isro

SCI/ENG "C"

Sep 2009 – Jul 2011 · 1 yr 10 mos · Ahmedabad

Design of IRNSS receiver using FPGA/embedded processor.
Development in C++ for Xilinx EDK.
QPSK Demdulator on Xilinx EDK/ISE using co-design
DSP Algorithm development. Study and Implementation of various DSP blocks on Xilinx SDK
Using board support package by Xilinx
Unix/Shell Scripting
Digital PLL implementation and profiling on SDK
Viterbi decoder and block de-interleaver on SDK.