Jyothinath C

Software Engineer

Bengaluru, Karnataka, India10 yrs 2 mos experience

Highly Stable

Key Highlights

Expert in ASIC and Physical Design processes.
Proven track record with top semiconductor companies.
Master's degree in VLSI Systems Design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.

Contact

Skills

Core Skills

SynthesisPhysical Design

Other Skills

FloorplanningPlacementClock Tree SynthesisRoutingStatic Timing AnalysisEMIRPhysical VerificationDRCLVSVerilogSoCTCLC++CLinux

About

Experienced System-on-Chip Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Synthesis & PnR (ASIC). Strong engineering professional with a Master's degree focused in VLSI Systems Design from JNTUA College of Engineering, Anantapur.

Experience

10 yrs 2 mos

Total Experience

2 yrs 7 mos

Average Tenure

2 yrs 5 mos

Current Experience

Nvidia

Sr Physical Design Engineer

Jan 2024 – Present · 2 yrs 5 mos · Bengaluru, Karnataka, India · Hybrid

Google

Silicon Engineer

Oct 2021 – Apr 2023 · 1 yr 6 mos · Bengaluru, Karnataka, India

On a short note, my primary responsibility is the Synthesis & physical design process involving the transformation of RTL to foundry specified GDSII description involving steps like Synthesis ,Floorplanning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, EMIR &Physical Verification (DRC,LVS) for realizing Google Pixel chip SoCs.

SynthesisPhysical DesignFloorplanningPlacementClock Tree SynthesisRouting+5

Intel corporation

Soc Design Engineer

Jun 2018 – Oct 2021 · 3 yrs 4 mos · Bengaluru, Karnataka, India

SOC Design Engineer :
On a short note, my primary responsibility is the Synthesis & physical design process involving the transformation of RTL to foundry specified GDSII description involving steps like Synthesis ,Floorplanning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, EMIR &Physical Verification (DRC,LVS) for realizing Advanced Intel Server and GPU SoCs.

SynthesisPhysical DesignFloorplanningPlacementClock Tree SynthesisRouting+5

Amd

3 roles

ASIC Physcial Design Engineer - II

Jul 2016 – Jun 2018 · 1 yr 11 mos

ASIC Physical Design Engineer - I

Jun 2015 – Jun 2016 · 1 yr

Physical Design :
On a short note, my primary responsibility is the physical design process involving the transformation of Gate Level Netlist description to foundry specified GDSII description involving steps like Floorplanning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, Physical Verification (DRC,LVS) for realizing next generation low power AMD APU SoCs.

Physical DesignFloorplanningPlacementClock Tree SynthesisRoutingStatic Timing Analysis+3