Jun 2025 – Present · 11 mos · United States · Hybrid

• Spearheading the ReRAM technology roadmap, focusing on innovative product introductions and market strategies.
• Fostering strong relationships with foundries and customers to drive market adoption of cutting-edge memory technologies.
• Collaborating with cross-functional teams to ensure alignment on product development and go-to-market initiatives.

Apr 2024 – Dec 2025 · 1 yr 8 mos · United States · Hybrid

Apr 2024 – Dec 2025 · 1 yr 8 mos · United States · Hybrid

• Building advanced AI algorithms for financial and behavioral patterns in fin tech industry

Jul 2023 – Present · 2 yrs 10 mos · Dallas, Texas, United States · Hybrid

• Advise on innovation and research in nanotechnology and space.

Jan 2022 – Aug 2022 · 7 mos · United States · Remote

• Thin film process optimization and lab to fab scaling

Jan 2021 – Dec 2025 · 4 yrs 11 mos · Florida, United States

• iQi, Inc is the developer of an IOT Air Quality Sensor platform designed to keep building occupants safe by reducing the risk of airborne infections and pollutants in air by automatically regulating air quality parameters.
• With their patent pending technology and an unique validated approach it uses A.I. & Machine learning to create indoor environments with temperatures, humidity levels, and reduced carbon dioxide to keep the occupants safe from Airborne infections, molds, allergies, etc… iQi has a huge arsenal of talent with extensive research experience in air quality & safety.
• iQi improves occupant’s productivity, comfort and safety while enabling building owners to reduce their energy bills on HVACs.

Aug 2020 – Apr 2024 · 3 yrs 8 mos · Atlanta Metropolitan Area · Hybrid

• Led the development of a proprietary Rapid Testing Semiconductor device for viral detection from saliva, transitioning it from concept to volume production.
• Managed the process development team and third-party relationships with premier labs, including Georgia Tech (IEN) and foundries, ensuring seamless collaboration.
• Oversaw the transition to high-volume manufacturing, implementing efficient production processes to meet market demands.

Jul 2019 – Jul 2021 · 2 yrs · Hyderabad, Telangana, India

• iVIS - Intensive Vigilance and Intervention System, was started by a group of highly successful entrepreneurs with prior experience in CCTV domain in USA/UK and Canada. Their primary aim was to use innovation to prevent theft and vandalism while making it affordable to all businesses.
• Current investors in iVIS originally cofounded Provigil Inc of the USA in 2007. They have exited that company in a transaction with Riverside capital, a private equity company based out of New York in 2015. iVIS has since acquired multiple clients in India (more than 20,000 locations) over the last few years.
• iVIS believes that prevention of theft and vandalism takes precedence over “merely watching and reporting theft”. One of the first groups to propose and deliver remote interventions via internet to deter theft, iVIS has since evolved with time to integrate various IOT technologies to improve efficiency and reduce expenses.

Apr 2019 – Apr 2021 · 2 yrs · Irving, Texas, United States

• Edbrix helps build a foundation for modern staff and student support in your district. Create a customizable, end-to-end solution that supports student learning and educational experiences. In one centralized platform, support instruction, administration, professional development, and more.
• Edbrix helps any educational organization, business industry, instructor, institute and/or organization to share, archive, publish, evaluate, assess and collaborate knowledge online as well as offline using the powerful platform of Google.

Dec 2018 – Dec 2020 · 2 yrs · Gilbert, Arizona, United States

• A joint effort to build magnetic equipment and solutions for Magnetic Random Access Memory(MRAM) for high thruput and high performance Magnetic Tunnel Junctions(MTJ) essential for the industry.

Jan 2016 – Dec 2020 · 4 yrs 11 mos · Santa clara,CA

• Developed IoT technology and a comprehensive product roadmap to enhance the golfing experience through AR and VR, successfully restructuring the business and expanding operations internationally.
• Introduced advanced magnetic sensors to golf applications, expanding remote interactive live coaching capabilities.
• Formed strategic partnerships with industry leaders such as Arrow Electronics, Flightscope, and TopGolf.

Nov 2012 – Jan 2016 · 3 yrs 2 mos · Santa Clara,CA

• Directed the go-to-market strategies and operations for TAS-MRAM, achieving over 90% yield and shipping the first million TAS sensors.
• Reduced lead time by fivefold and wafer transit time by over 60 days through critical process optimizations.
• Implemented standard operating procedures for mask making and wafer recycling.
• Established and managed the Product Engineering Test and Support (PETS) team, centralizing resources and overseeing global engineering teams.
• Developed MRAM demo boards and negotiated cost reductions in technology development.

Jan 2003 – Nov 2012 · 9 yrs 10 mos · Santa clara

• Successfully developed Field Induced MRAM technology from 350 nm to 18 nm, culminating in a successful exit for stakeholders.
• Raised substantial venture funding through Series A & B rounds, ensuring the financial stability and growth of the company.
• Secured an exclusive license for two fundamental MTJ patents from MIT, generating significant IP revenue.
• Delivered a 1 Mb MRAM on 6" 1P4M 350nm with access times of 20ns and developed the world's first 3Mb Display Driver IC in 130nm High Voltage 8" 1P6M.
• Successfully integrated MRAM in a 130nm Display Driver CMOS High Voltage all Aluminum process and developed a Reactive Ion Etching (RIE) process for etching MTJ down to 18 nm.
• Built and managed a multidisciplinary team of over 20 professionals, developed a robust MRAM patent portfolio consisting of 41 patents.
• Served on the Board of Directors of MagSil and the Advisory Board for the Translational Applications of Nanoscale Multiferroic Systems Center at UCLA.

Jul 2001 – Sep 2002 · 1 yr 2 mos · Torrance, CA · On-site

• Product Development: Developed the 10GBASE-SR LAN PHY Physical Coding Sub layer (PCS) chip, coding RTL
• for the Channel Align, Rate Adjust, and Deskew blocks for both Tx and Rx paths. Additionally, coded high-speed
• FIFO for rate adjust and channel align, as well as the MDIO block, and verified their functionality.
• Synthesis and Verification: Led the synthesis, static timing, and formal verification efforts, ensuring the design
• met all technical specifications and performance criteria.
• GHz Transient Regulator Controller: Coded the RTL for the GHz interface control state machine using Verilog,
• verified the MHz serial interface, and led the static timing effort using Prime Time. Developed the formal
• verification methodology using Chrysalis design verifier and generated test vectors for Advantest tester.
• Project Management: Managed the 10GBASE-R Physical Coding Sub layer (PCS) chip project, outsourcing
• backend design to third-party ASIC backend vendors. Developed detailed technical requirements for backend
• services, communicated with 15 vendors and their customers to prescreen, evaluated vendor bids for technical
• capability and cost efficiency, organized vendor presentations, and negotiated prices, saving $85,000 with better
• service terms.
• Outsourcing Strategy: Conceptualized and implemented a systematic approach to outsourcing GHz transient
• regulator design, representing the design team in face-to-face meetings with Atmel, Epson, and Samsung.
• Supported Epson synthesis, static timing, and place & route activities, managed Samsung backend and foundry
• activities, and performed on-site project management to accelerate the schedule.
• Training and Reliability: Trained engineers on the use of formal verification and static timing analysis tools,
• developed a reliability qualification plan, and achieved first-time success on silicon.
• Results – Created over $1M▲ value by turning around a critical project and retained an important customer
• investor.

Jan 2001 – Dec 2001 · 11 mos · Long Beach, California, United States · On-site

• High-Speed Design: Designed 40Gbps and 10Gbps Forward Error Correction devices for SONET/SDH, ensuring robust performance for long-haul optical network applications.
• Team Leadership: Hired and managed a team of ASIC engineers, overseeing the entire ASIC design cycle from RTL coding to synthesis, static timing analysis, and foundry interface.
• Comprehensive Project Management: Managed the entire ASIC design cycle, including RTL coding, synthesis, static timing analysis, and foundry interface, ensuring timely and successful project completion.
• Results – Successfully designed a 40Gbps and 10Gbps Forward Error Correction device.

Jan 1996 – Jan 2001 · 5 yrs · Newport Beach, California, United States · On-site

• Single Chip Modem and ASIC Microcontroller: Designed and optimized signal integrity, noise analysis, synthesis, and static timing of ASIC blocks, ensuring robust performance and reliability.
• Embedded FLASH Development: Designed high voltage control circuitry and implemented the Simultaneous Read Write feature for 4 and 8 Meg embedded FLASH. Oversaw a 3-member layout design team and collaborated with external experts to develop high voltage generation and control circuitry.
• Layout Coordination: Coordinated the layout of high voltage blocks and the full chip, serving as a knowledge bridge between design and technology development teams. Authored the "Layout Designers' Guide to FLASH Process Technology" for internal use.
• HDSL2 Transceiver and Framer: Led the static timing sign-off using Prime Time, managed all ECO and optimization of the clock tree for the ZipWire2-HDSL2 Transceiver and Framer.
• PHY - 10G Very Short-Range Converter (VSRC): Led the transistor-level optimization of the Serializer and De-serializer, conceptualized and incorporated a transistor-level SPICE methodology for critical ASIC blocks.
• Multiservice Access Products: Conducted signal integrity and clock skew analysis for the full custom chip AnyPort: CSMV/6, ensuring design robustness.
• Digital Signal Processor: Achieved signal integrity and design robustness on custom building blocks for the Digital Signal Processor.
• ARM Processor Test Chips: Led timing analysis of ARM7, ARM7TDMI, ARM9TDI, and ARM940T in 0.25 µm and 0.18 µm processes. Coordinated engineering and production testing of ARM test chips, resolving design implementation issues in collaboration with ARM, UK engineers.
• Results – Created over $4M▲ value by identifying major design flaws and process bugs that jeopardized customer products.
• Received Team Award for the above achievement

Jan 1995 – Jan 1996 · 1 yr · Noida, Uttar Pradesh, India · On-site

• Static RAM Design: Designed and developed Static RAMs for low power applications, ensuring efficient and reliable memory solutions.
• Process Test Structures: Designed and implemented SRAM-related process test structures to enhance manufacturing quality and performance.
• CAD Coordination: Served as the Coordinator of the CAD-Center of Expertise, assisting upper management in making informed purchase decisions for VLSI CAD tools.
• Procurement Leadership: Led the procurement of computer hardware and CAD tools, ensuring the availability of necessary resources for design and development.
• Global Collaboration: Collaborated with STM engineers and managers from Italy, France, and Singapore to synchronize the Memory Products Group in India with other STM design centers worldwide.
• Technical Training: Lectured on "VLSI Process Development" to new graduates, sharing expertise and fostering the next generation of engineers.
• Results – Over $200k▲ in value through quality and performance improvements and procurement of better hardware and CAD tools.

Jan 1990 – Jan 1995 · 5 yrs · Chandigarh, India · On-site

• Process Development: Developed 2µm and 1.25µm CMOS process and integration schemes, as well as a 2µm CCD CMOS process, ensuring advanced manufacturing capabilities.
• Device Modeling: Led the device modeling of linear imagers for space applications, contributing to the development of high-performance imaging technology.
• Simulator Development: Conceptualized, initiated, and developed a comprehensive CCD one-dimensional device simulator (BRISK), saving thousands of dollars in simulation tool costs by creating an in-house solution.
• Collaboration with Space Applications Center: Coordinated with officials at the Space Applications Center, Ahmedabad, India, to define linear imager specifications and held technical discussions during its development.
• Infrared Imager Design: Developed the concept and design of an Infrared Imager for the Space Applications Center, enhancing the capabilities of space-based imaging systems.
• Noise Research: Researched flicker noise in various process generations to correlate with process parameters, improving the understanding and control of noise in semiconductor devices.
• SPICE Parameter Extraction: Performed extraction of BSIM SPICE parameters for different generations of CMOS processes, contributing to accurate device modeling and simulation.
• Cross-Functional Team Contributions: Contributed to cross-functional BiCMOS, High Voltage, and 0.8µm technology development teams, fostering innovation and collaboration.
• Technical Committee Membership: Served as a member of the technical committee to evaluate the technical aspects of microelectronics manufacturing equipment for setting up a Class 10 VLSI fabrication facility.
• Process and Device Simulation: Simulated processes and devices using SUPREM and MINIMOS tools, ensuring accurate modeling and optimization of semiconductor processes.
• Achievements – Designed an indigenous IR imager for satellite applications and cut cost by 10x▼. Also, developed a 2D CCD simulator worth $80k▲.

Jan 1989 – Jan 1990 · 1 yr · Mettur dam,India · On-site

• Quality Assurance Leadership: Managed a team of 6 technicians responsible for the quality assurance of silicon wafers, ensuring high standards and reliability.
• Implementation of ASTM Procedures: Implemented ASTM (American Society for Testing and Materials) quality control procedures for monocrystalline silicon, enhancing the overall quality assurance process.
• Customer Engagement: Informed, educated, and convinced high-level technical teams from major customers about the quality assurance procedures adopted by the company and its ability to implement them effectively.
• Defect Analysis and Elimination: Implemented quality assurance procedures for estimating crystal defect density, carbon, and oxygen contamination, and identifying and eliminating causes of crystal defects.
• Chemical Texturization Research: Conducted a study on the chemical texturization of silicon wafers for solar cells, perfecting a recipe that could be used in large-scale production of solar cells.
• Crystal Growth Techniques: Pulled silicon crystals using Czochralski (CZ) and Float Zone (FZ) crystal growth techniques, contributing to the development of high-quality silicon wafers.
• Results – Created over $500k▲ in value by reducing production downtime from 24h to under 2h▼. Increased production by over 50%▲ and predictably created zero defect wafers by instrumenting quality gates.