Mamta Parab — Product Engineer

I am a Product Engineer in the EDA industry, working on cutting-edge tools for static timing analysis, clock domain crossing and signoff. My core expertise lies in constraint debugging, tool validation, designing new features and bridging the gap between engineering and customer success. At the intersection of design and innovation, I work closely with Cadence’s internal R&D teams and global customers to identify tool discrepancies, and propose and validate enhancements that drive real-world impact. My background in Electrical and Computer Engineering, along with hands-on experience with Cadence and Synopsys flows, helps me contribute effectively across RTL to GDS. I’m passionate about simplifying complex design challenges, enhancing EDA tool usability, and exploring how AI/ML can reshape constraint signoff in the near future. Always curious, always learning. Let’s connect over shared interest in static timing, CDC, and the future of VLSI innovation.

Stackforce AI infers this person is a Product Engineer in the EDA industry with a focus on VLSI and embedded systems.

Location: San Jose, California, United States

Experience: 4 yrs 10 mos