M

Manish Rai

Software Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in SoC architecture and performance optimization.
Proven track record in pre-silicon performance analysis.
Strong background in multimedia and system performance modeling.

Stackforce AI infers this person is a Semiconductor Performance Engineer with expertise in SoC architecture and optimization.

Contact

Skills

Core Skills

Soc ArchitecturePerformance Engineering

Other Skills

Pre-Silicon Performance AnalysisArchitecture OptimizationSystem Performance ModelingNOC DesignMMU DesignDDR DesignMultimedia Performance AnalysisCC++PythonEmbedded SystemsMatlabMicrosoft OfficeLaTeXVHDL

About

Currently working with AMD Compute AI/graphics Performance team. Worked with Qualcomm's SoC architecture Performance team using TLM and evaluate the performance, Area optimization, design optimization and power of next generation chipsets for Smartphone, PC and IoT products.

Experience

8 yrs 8 mos

Total Experience

2 yrs 6 mos

Average Tenure

1 yr 2 mos

Current Experience

Renesas electronics

Staff Engineer

Apr 2025 – Present · 1 yr 2 mos · Noida, Uttar Pradesh, India · On-site

Amd

Senior Silicon Design Engineer

Feb 2022 – Mar 2025 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Qualcomm

SoC Architecture Performance Engineer

Sep 2018 – Feb 2022 · 3 yrs 5 mos · banglore

Responsible for end to end Pre-Silicon Performance Analysis
for Snapdragon Mobile, Automotive and IOT Platforms.
Working on ideas of architecture and design changes that
can optimize the overall power/performance/Area for the
chipset
Developing and integrating system performance model for
complete SOC
Working on NOC, MMU designs, DDR design and its
performance aspects at SOC level
Working on Multimedia domains like Camera, Video, GPU
and its performance at system level
Focus on architecture definition, exploration and modelling
of the multimedia, memory subsystems, and Quality of
Service (QoS) solutions

Pre-Silicon Performance AnalysisArchitecture OptimizationSystem Performance ModelingNOC DesignMMU DesignDDR Design+3

Co-curricular and academic interaction council (caic),iit delhi

convenor

Apr 2017 – Apr 2018 · 1 yr · New Delhi Area, India

Education

Indian Institute of Technology, Delhi

Master of Technology (M.Tech.) — Telecommunications technology

Jan 2016 – Jan 2018

AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD

Bachelor of Technology (B.Tech.)

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