M

Matteo Giovannelli

Software Engineer

Milan, Lombardy, Italy2 yrs experience
Highly Stable

Key Highlights

  • Experienced in Analog Design Engineering.
  • Proficient in FPGA and ASIC design.
  • Strong background in circuit design and simulation.
Stackforce AI infers this person is an Analog Design Engineer with expertise in semiconductor and circuit design.

Contact

LinkedIn

Skills

Other Skills

MatlabSimulinkMEMSASICprogettazione circuiti integratiProgettazione circuiti stampatiCadence VirtuosoAltiumFPGAXilinx VivadoVHDLprogetti su FPGAprotocollo AXI4CLingua inglese

Experience

2 yrs
Total Experience
2 yrs
Average Tenure
2 yrs
Current Experience

Synopsys inc

Senior Analog Design Engineer

Jun 2024 – Present · 2 yrs

Arlanis reply it

Consulente

Jul 2023 – Dec 2023 · 5 mos · Milano, Lombardia, Italia

Education

Politecnico di Milano

Laurea Magistrale LM — ingegneria elettronica

Mar 2021 – Apr 2024

Politecnico di Milano

Laurea breve — Ingegneria elettronica

Jan 2017 – Jan 2021

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