Jun 2022 – Present · 3 yrs 11 mos

• ATE Hardware Development (Sort and Class)
• Collaborated with cross-functional teams to develop and validate Automated Test Equipment (ATE) loadboards for Intel package and silicon testing.
• Led working groups to manage and implement ATE loadboard design changes and requests across multiple product lines.
• Executed hardware board First Article Inspections (FAI) to ensure validation and readiness for high-volume engineering release.
• Utilized industry-standard software including Argus, Cadence Allegro, and Mentor Graphics for the validation of TIU/SIU layout designs and T-spec files.
• Managed external vendor relationships from initial engagement to product execution, consistently meeting project schedules.
• Leveraged expertise in the Advantest V93K CTH handler ATE tester platform.

Jun 2020 – Jun 2022 · 2 yrs

• Factory Tools Development
• Failure Analysis Support: Employ Intel-standard tools to identify failing pins on the package substrate during various testing phases (Class Test, validation, production), using tester channel numbers for precise physical location.
• Global Collaboration: Coordinate with cross-functional engineering teams (Product, Production, FA, QRE) across Intel's worldwide facilities to manage product setups and troubleshoot issues.
• Design Validation: Validate TIU and substrate designs through schematic and layout analysis using Cadence Allegro and Mentor Graphics xPCB Viewer.
• Process Improvement: Drive collaborative working groups with stakeholders to enhance existing tools and address operational requests.

Jun 2016 – Jun 2020 · 4 yrs

• Sort/Class Test Program Development
• Developed, integrated, and validated test programs for Intel Server products, collaborating closely with Content and Module owners (Scan, Array, PLL, Reset, etc.) throughout the development lifecycle.
• Supported comprehensive testing across both Class Test (unit/package) and Sort Test (wafer) phases within the Manufacturing Validation Engineering division.
• Delivered production-ready test programs, consistently achieving high yield rates and minimized test times.
• Standardized and distributed efficient workflows and Best Known Methods (BKMs) to stakeholders, leading to significant test time reductions during first silicon validation.
• Facilitated pre-silicon mock debug sessions, utilizing learnings from previous silicon stepping failures to prevent recurring issues.
• Drove product working groups and collaborated with stakeholders on reject validation processes to ensure all Quality Assurance (QA) requirements and timelines were met.
• Leveraged expertise with Automated Test Equipment (ATE) platforms, including Advantest CMT/HDMX, for both package and wafer level testing.
• Performed in-depth data and results analysis using specialized tools (Trace, CB, SQLP, Excel) to drive continuous improvement.
• Executed critical debugging, implemented recovery flows, profiled test instance currents, and resolved pattern/preamble/plist failures to optimize program quality and efficiency.