Namhoon Kim

Director of Engineering

San Jose, California, United States26 yrs 4 mos experience

AI ML PractitionerAI Enabled

Key Highlights

Expert in silicon development and execution.
Proven leader of geographically distributed teams.
Innovator in Power/Timing/Noise analysis.

Stackforce AI infers this person is a leader in semiconductor engineering and EDA with a focus on innovative solutions.

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Skills

Core Skills

Power/timing/noise AnalysisPhysical DesignProject PlanningIp DevelopmentCad SolutionsSilicon Lifecycle ManagementPower EstimationTiming Sign-offAsic MethodologiesFpga Timing ClosureStatic Timing AnalysisTool DevelopmentHigh-level Synthesis

Other Skills

Methodology/CADIncubationPrototype executionAI machine learningStatic timing analysis toolsVerilogPerlCFPGAASICC++PythonSignal IntegrityTCLArchitecture

About

Specialties: Expertise in silicon development from strategic planning to execution Building/Leading geographically distributed teams resulting in collaborative dynamics Expert in Power/Timing/Noise analysis, characterization and sign-off Machine Learning in EDA

Experience

26 yrs 4 mos

Total Experience

6 yrs 4 mos

Average Tenure

1 yr

Current Experience

Cisco

Senior Director, Hardware Engineering

Jun 2025 – Present · 1 yr · San Francisco Bay Area

Leading Physical Design, Methodology/CAD org for Cisco's core Switching, Routing and Wireless products

Power/Timing/Noise analysisPhysical DesignMethodology/CAD

Synopsys inc

2 roles

Senior Director, R&D Engineering

Promoted

Jan 2024 – Jun 2025 · 1 yr 5 mos · San Francisco Bay Area

Led SLM hardware horizonal organization to scale IP development functions with innovative solutions
Served as Chief of Staff in SLM Hardware Group to service SLM business needs and to support project planning, incubation, prototype, execution and productization

IP developmentProject planningIncubationPrototype execution

Director, CAD Engineering

Jul 2022 – Jan 2024 · 1 yr 6 mos · San Francisco Bay Area

Led global teams to create innovative CAD solutions to solve tough problems efficiently in the area of Silicon Lifecycle Management (SLM)

CAD solutionsSilicon Lifecycle Management

Intel corporation

2 roles

Senior Design Manager

Nov 2016 – Jul 2022 · 5 yrs 8 mos · San Francisco Bay Area

Led global power team responsible for product planning, power estimation and optimization
Led cross functional teams responsible for full chip timing sign-off, multi-chip timing closure
Led the multi-corner/multi-mode block-level timing ECOs for PSG FPGA projects
Drove AI machine learning based EDA taskforce

Power estimationTiming sign-offAI machine learning

Principal Engineer

Aug 2012 – Oct 2016 · 4 yrs 2 mos · San Francisco Bay Area

Altera became part of Intel PSG:
Architected the overall ASIC and custom timing methodologies for Altera FPGA projects
Led FPGA timing closure and model generation taskforce
Drove correlation of pre-silicon timing results with silicon measurement

ASIC methodologiesFPGA timing closure

Oracle

Principal Software Engineer

Dec 2005 – Aug 2012 · 6 yrs 8 mos · San Francisco Bay Area

Led a tool development team for static timing/noise analysis and characterization of custom digital blocks and memories
Deployed STA clock path sign-off and SRAMs timing analysis tools for Sun Sparc CPU projects

Static timing analysisTool development

Samsung electronics

Senior Engineer

Aug 1997 – Jul 2003 · 5 yrs 11 mos

Led design methodology including High-level Synthesis, Advanced DV, and RTL to GDS
Developed schematic editor, static timing analysis, RTL analysis tools and other various in-house tools

High-level SynthesisStatic timing analysis toolsStatic timing analysis