Narayan Ranganathan

Director of Engineering

Bengaluru, Karnataka, India27 yrs 4 mos experience

Highly Stable

Key Highlights

Led development of Xeon acceleration technology.
Pioneered disaggregated FPGA solutions for cloud.
Expert in data center virtualization and architecture.

Stackforce AI infers this person is a Data Center and Semiconductor Architect with extensive experience in virtualization and system architecture.

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Skills

Core Skills

Engineering LeadershipArchitecture Specification

Other Skills

Prototype Software DevelopmentData CenterVirtualizationCpu design and microarchitecturex86/Xeon platform architecturemulti-coreOS internalsCpu functional validationData center manageabilityRASPower managementVMwareEnterprise SoftwareComputer ArchitectureDebugging

About

Specialties: Data center Virtualization, Cpu design and microarchitecture, x86/Xeon platform architecture, multi-core, OS internals, Cpu functional validation, Data center manageability, RAS, Power management

Experience

27 yrs 4 mos

Total Experience

25 yrs 10 mos

Average Tenure

1 yr 6 mos

Current Experience

Microsoft

Principal Engineering Manager

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

8 roles

Senior Principal Engineer, Systems Architecture Lab (Intel Labs)

Mar 2024 – Sep 2024 · 6 mos

Architect responsible for leading team to define roadmap and landing zone definition, develop architecture specification and deliver prototype software for Xeon acceleration technology like Intel Data Streaming Accelerator (first productized on 4th gen Intel Xeon cpus)

Engineering Leadership

Principal Engineer, Systems Architecture Lab, Intel Labs

Mar 2020 – Feb 2024 · 3 yrs 11 mos

Principal Engineer, Data Platforms Group

Mar 2017 – Mar 2020 · 3 yrs

As a platform architect and technologist, I was responsible for the development of innovative data center technologies through system architecture definition and development of functional prototypes. In this role, I led a small engineering team to define and deliver a working prototype for a disaggregated FPGA over RDMA (aka FPGA-overfabric, FPGA-oF) solution and led the development of accelerator disaggregation technology for the cloud, aka Accelerator-over-fabric (Accel-oF). My work involved publishing architecture specifications for FPGA-oF and Accel-oF, developing middleware that implemented the specification, and showcasing the technology with proof-of-concepts.

Platform Software Architect, Data Platforms Group

Aug 2015 – Mar 2017 · 1 yr 7 mos

Architecture and R&D for next generation server (Intel Rack Scale Design) platforms. As part of an exploratory project on disaggregated memory, I contributed to architecture definition and proof-of-concept development for a disaggregated memory solution at rack scale over Intel Omnipath fabric including partitioned global address space (PGAS) support.

Platform Software Architect, Data Center Group (DCG)

Promoted

May 2011 – Jul 2015 · 4 yrs 2 mos

Contributed to the technology development and pathfinding for various aspects of Intel Rackscale architecture, including server platform reliability (RAS) features like machine check recovery, Enhanced Machine Check Architecture (eMCA) and a novel platform firmware-based option for in-field error logging and diagnostics.
Participated in technical deep-dives with customers on usages and guidance for new technologies like Intel Optane memory, and developed an architecture specification to define use-case mapping of Intel Optane memory in SAP HANA.
Contributed to development of working prototypes resulting in successful demos at industry forums like the Intel Developer Forum (IDF) and Supercomputing conference (SC14).