Nikhil Sharma

Software Engineer

Bengaluru, Karnataka, India3 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Physical Design Integration and CAD Engineering.
Proficient in SoC Design Verification and RTL Coding.
Recognized for contributions in SoC verification and DFD projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in CAD and SoC verification.

Contact

Skills

Core Skills

Physical Design IntegrationCad EngineeringDesign Flow DevelopmentSoc Design VerificationRtl Coding

Other Skills

Synopsys Design CompilercalibreCadence VirtuosoSynopsys IC CompilerSystemVerilogUniversal Verification Methodology (UVM)UVMVHDLVerilogVery-Large-Scale Integration (VLSI)Digital ElectronicsLinuxMicrosoft Azure SkillMicrosoft OfficeC++

About

As a Physical Design Integration Engineer at Intel Corporation, I apply my CAD and SoC expertise to handle design flow development, chip layout circuit design integration, and device evaluation, characterization and Tape-in. I have been working with Intel since June 2022, starting as a SoC Design Engineer and then moving to the CAD in Feb 2023 and then Physical Design Integration team in Nov 2023. I have a Master of Technology in Electronics and Communication from Dr B R Ambedkar National Institute of Technology, Jalandhar, where I gained proficiency in VHDL, Verilog, System Verilog, UVM, Linux, C and C++, Python, and MATLAB. I also have multiple certifications in data processing, C C++, and computer vision applications. I have received recognition for my contributions in SoC verification, DFD VISA block, and SRF DFD VAL roadmap. I am a quick learner, energetic, and team player, who strives to deliver quality results and innovative solutions for the organization.

Experience

3 yrs 9 mos

Total Experience

3 yrs 9 mos

Average Tenure

3 yrs 9 mos

Current Experience

Intel corporation

4 roles

Physical Design Integration Engineer

Promoted

Nov 2023 – Present · 2 yrs 7 mos

Synopsys Design CompilercalibreCadence VirtuosoPhysical Design IntegrationCAD Engineering

CAD Engineer

Feb 2023 – Oct 2023 · 8 mos

Developed and applied computer aided design (CAD) engineering methods theories and research techniques in the investigation and solution of technical problems.

calibreCadence VirtuosoSynopsys IC CompilerCAD EngineeringDesign Flow Development

SoC Design Verification Engineer

Jun 2022 – Jan 2023 · 7 mos

Key involvement in working within the System on Chip (SoC) design domain and contributing towards working in server chip and client chip projects.
Diligent in handling Design for Debug (DFD) and working on Visualization of Internal Signal Architecture (VISA) related testcases and debugging them using Verdi tool.
Well-versed with system Verilog and UVM, Proficient in RTL coding using VHDL, Verilog and System Verilog.
Debugged the errors like UVM_ERROR and sequence error, etc.

SystemVerilogUniversal Verification Methodology (UVM)SoC Design VerificationRTL Coding

SoC Verification Intern

Jul 2021 – May 2022 · 10 mos

Managed working in System on Chip (SoC) Verification domain as an intern at Intel.
Executed work in Soc Verification for the Visualization of Internal Signal Architecture (VISA) in Design for Debug (DFD).
Worked in VISA and managed System Verilog pattern generator testcases for RTL Design Under Test (DUT) writing and modification.
Handled the regression of testcases, manually checked failed testcases and their waveforms using Verdi tool.