Nitesh Kumar — Product Engineer
Hi, Thanks for visiting my profile. As a DFT Engineer, My Work Experience are- *Insertion of OCC, EDT and SCAN at the block level. *Uncompressed and Compressed mode of ATPG at block level & Chip level. *Handling of multiple OCCs at block level. * Coverage Analysis *Timing/No-timing Scan simulation for both stuck-at and TDF. *Scan pattern Re-targetting and Scan simulation. *Working closely with the STA team on finalizing Dft constraints. *Done Occ clock frequency verification by writing verilog code & monitoring with simulation log,no need for a wave dump. *Performed formality,LEC check before handing over DFT inserted netlist to the PD team. *Worked on Synthesis with genus tool. *Done experimental and post-dft ECO's in gate-level netlist. *Responsible for delivering VCD dump to PD team to check IR drop. *Responsible for delivering final ATE patterns for stuck-at and TDF to the tester team. *Providing post-silicon support for the delivered patterns. *Performed diagnosis of failing patterns based on tester team feedback. Additional Info- *Eager to learn and grow in the field of Dft.
Stackforce AI infers this person is a DFT Engineer specializing in VLSI and ASIC design verification.
Location: Noida, Uttar Pradesh, India
Experience: 5 yrs 3 mos
Skills
- Atpg
- Scan Insertion
Career Highlights
- Expert in DFT methodologies and ATPG processes.
- Proficient in Verilog and synthesis tools.
- Strong background in coverage analysis and scan insertion.
Work Experience
Tecquire Solutions Pvt Ltd
DFT Engineer (5 yrs 3 mos)
Education
Bachelor of Engineering at CHANDIGARH UNIVERSITY
Post Graduation Design and Verification Trainee at Futurewiz Vlsi training institute Noida
Intermediate at Bokaro Public School
10th at Wetge Public School, Bokaro
6 to 8 at Buds Garden School, Rajganj, Dhanbad
