Jun 2021 – Present · 5 yrs · San Diego County, California, United States

• Work on machine vision and Integrate deep learning into the self-driving vehicles/drones
• Develop an in-memory computing platform with the novel high-speed arithmetic approach
• Co-author: Artificial Intelligent Hardware Design - Challenges and Solutions, published by Wiley in July 2021
• Co-author: Understanding Artificial Intelligence: Fundamentals and Applications, published by Wiley in March 2022

Aug 2012 – May 2021 · 8 yrs 9 mos · Greater San Diego Area

• Work on nanotechnology development for process/design integration, focus on PPA and clock tree optimization
• Develop analog DFM guideline for advanced FinFet design
• Automate timing path analysis and support instance based IR drop/noise timing co-simulations
• Reduce the overall SPICE runtime (> 100X) through fast parallel simulation approach

Jan 2011 – Jan 2012 · 1 yr · Toronto, Canada Area

• - Work on 40nm analog macro layout design with DFM support

Jan 2008 – Jan 2010 · 2 yrs · Hsinchu, Taiwan

• Work on 28nm HKMG process Restricted Design Rules (RDR) and Design For Manufacturability (DFM) Rules development
• Develop Layout Control Monitor (LCM) to identify HKMG Layout Dependent Effect (LDE) process/model issues
• Develop innovative 3D-IC architecture using Through Silicon Via (TSV) approach and incorporate pseudo 3D IC flow into current SoC design

Jan 2006 – Jan 2007 · 1 yr · Ontario, Canada

• Promote DFY initiatives with LRC, CMP and CAA for yield improvement
• Implement Defect Search Engine (DSE) to identify potential short/open location for Physical Failure Analysis (PFA) studies

Jan 2001 – Jan 2006 · 5 yrs · Ontario, Canada

• Establish chip integration team to focus on all signal integrity issues: crosstalk, electromigration and IR drop issues
• Lead full chip sign-off projects to resolve all physical design issues before tapeout
• Work on design migration projects for multiple foundry supports

Jan 1999 – Jan 2001 · 2 yrs · Ontario, Canada

• - Develop wirebond and flip chip Power Distribution Network (PDN) for chip implementation, include Redistribution Layer (RDL) design

Jan 1996 – Jan 1999 · 3 yrs · Ontario, Canada

• Establish standard cell team to develop special cells, include gated clock latch, quad flop and ECO cell
• Develop single/dual port memory compiler

Jan 1995 – Jan 1996 · 1 yr · Ontario, Canada

• - Implement Custom Own Tooling (COT) for physical design