Parthiban Dhanapal

DevOps Engineer

Chennai, Tamil Nadu, India14 yrs 8 mos experience

Highly Stable

Key Highlights

Over a decade of experience in physical design engineering.
Expertise in block level and top level PD and STA closure.
Contributed to multiple tape-outs, including cutting-edge 3nm technology.

Stackforce AI infers this person is a Physical Design Engineer with expertise in advanced semiconductor technologies.

Contact

Skills

Other Skills

Cadence VirtuosoCLinuxPerlMicrosoft OfficeMicrosoft ExcelMicrosoft WordTCLMagma

About

Physical design engineer since 2011. Proficient in block level and top level PD and sta closure. Have been part multiple TO at different nodes, with latest being 3nm.

Experience

14 yrs 8 mos

Total Experience

4 yrs

Average Tenure

2 yrs 7 mos

Current Experience

Nvidia

2 roles

Principal Physical Design Engineer

Promoted

Mar 2026 – Present · 3 mos

Senior Physical Design Engineer

Nov 2023 – Mar 2026 · 2 yrs 4 mos

Qualcomm

2 roles

Staff Engineer

Dec 2019 – Nov 2023 · 3 yrs 11 mos

Senior Lead Engineer

Oct 2016 – Dec 2019 · 3 yrs 2 mos

Wireless communications startup

Senior Engineer

Apr 2016 – Sep 2016 · 5 mos

Nvidia

2 roles

Senior Physical Design Engineer

Promoted

Oct 2014 – Mar 2016 · 1 yr 5 mos

Physical Design Engineer

Jul 2011 – Sep 2014 · 3 yrs 2 mos

Partition Place and Route

Education

National Institute of Technology, Tiruchirappalli

Master of Technology (M.Tech.) — VLSI System

Jan 2009 – Jan 2011

Easwari Engg College, Chennai

Bachelor of Engineering (B.E.) — Electrical and Electronics Engineering

Jan 2005 – Jan 2009

Stackforce found 100+ more professionals with Cadence Virtuoso & C

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