Paul Chung

Software Engineer

United States2 yrs 4 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Proven expertise in firmware development for SSDs.
Strong debugging and problem-solving skills.
Rapidly promoted to Senior Engineer within 1.5 years.

Stackforce AI infers this person is a Firmware Engineer specializing in SSD technology and embedded systems.

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Skills

Core Skills

CC++

Other Skills

NVMeDRAM ManagementAtlas RegisterationData VisualizationMATLABSignal ProcessingDigital Signal ProcessingImage ProcessingCloud ServerCompiler ConstructionJdecGitHubCI/CADDR/LPDDR PHYHailo AI

Experience

2 yrs 4 mos

Total Experience

1 yr 9 mos

Average Tenure

7 mos

Current Experience

Amd

2 roles

Silicon Design Engineer II

Jan 2026 – Present · 4 mos · Santa Clara, California, United States · On-site

Firmware Engineer Intern

Jun 2025 – Sep 2025 · 3 mos · Santa Clara County, California, United States · On-site

1. Gained an understanding of JEDEC DDR5/LPDDR5, PHY firmware, and Topaz module specifications.
2. Enhanced test processes and architecture by integrating ESID harness tests and incorporating board delays into the AM regression workflow, leading to improved test efficiency and firmware stability.
3. Demonstrated strong debugging and learning skills by effectively resolving failures occurring in release gate and AM regression tests, contributing to foundational firmware debugging and architecture optimization.
4. Showcased initiative, rapid individual progress, and strong collaboration and problem-solving skills, quickly ramping up to contribute effectively and earning a high performance evaluation by the end of the internship.

CC++

Solid state storage technology corporation

Firmware Engineer

Nov 2021 – Aug 2023 · 1 yr 9 mos · Hsinchu City, Taiwan, Taiwan · On-site

1. Solid-State Drive FW development with PCIE Enterprise Gen3 / Gen4 Client SSD (two projects).
2. Comprehensive understanding of the SSD knowledge, read/write flow (cache), including Logical(Physical) data address, L2P table update, SPB management.
3. Design and maintenance frontend feature to align with NVMe spec - Namespace protocols( namespace mapping mechanism to enhance 35% of disk performance.), format, persistent event log, device self test, AER, read only mode, and other frontend features.
4. Maintain the DRAM memory allocation and management for our firmware usage.
Modify FW code into more flexible version that can dynamic suitable into different disk size & different DRAM.
5.Demonstrating strong collaboration and communication skills, along with exceptional debugging abilities and well documentation skills, qualified for a promotion to Senior Engineer within only one and a half years.

CC++