Pradeep Maurya

Software Engineer

Bengaluru, Karnataka, India10 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Architected automated validation frameworks for high-performance systems.
Led cross-geo teams to deliver reliable networking subsystems.
Expertise in Linux kernel and C++ systems programming.

Stackforce AI infers this person is a Senior Systems Software Engineer specializing in Networking and Storage Infrastructure.

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Skills

Core Skills

NetworkingC++AutomationStorage

Other Skills

CIPSecAESTCP/IPLow-level NetworkingLinux/UNIXMultithreadingSTLSystems ProgrammingPythonLinuxNVMeSATAREST APIsGIT

About

Senior systems software engineer with 8+ years building high-performance infrastructure at Intel and ShoreTel — across Linux kernel internals, C++ systems programming, networking subsystems, and hardware–software validation at scale. At Intel, I architected and owned an end-to-end automated validation framework covering NVMe, SATA, UFS, and system power management — tested under real-world and failure-driven workloads across storage, memory, and platform subsystems. This gave me deep hands-on experience with storage I/O paths, kernel driver behavior, and low-level debugging of hardware–software interactions. At ShoreTel, I built Linux-based networking infrastructure and worked across TCP/IP networking, multithreaded systems programming, and platform reliability engineering. Technical depth: Linux kernel · C++ (11/14/17) · Golang · TCP/IP · DPDK · NVMe / NVMe-oF · eBPF · io_uring · multithreading · distributed systems · storage subsystems · performance engineering · infrastructure automation · packet processing. Currently open to senior infrastructure roles in kernel engineering, network software, storage systems, or AI infrastructure — Bengaluru, Hyderabad, or remote.

Experience

10 yrs 3 mos

Total Experience

5 yrs 1 mo

Average Tenure

8 yrs

Current Experience

Intel corporation

2 roles

Software Engineer

May 2021 – Present · 5 yrs · On-site

Led system-level validation of high-throughput Ethernet packet processing pipelines (MAC/PHY datapath), ensuring functional correctness, protocol compliance, and subsystem stability under heavy traffic workloads.
Designed and implemented a C++ low-level validation framework on Linux, interfacing directly with packet datapaths, hardware registers, DMA engines, and interrupt paths to verify networking subsystem behavior.
Developed and automated 100+ reusable packet-flow validation scenarios using C++ and internal libraries, expanding regression coverage and enabling scalable validation across multiple networking silicon products.
Investigated packet-path failures, throughput limitations, and latency bottlenecks, performing deep debugging across datapath components and collaborating with firmware, hardware, and architecture teams to resolve integration issues.
Built automation infrastructure for large-scale regression testing, significantly improving validation throughput and enabling continuous verification of Ethernet and TCP/IP traffic flows.
Enabled cross-product reuse of the validation framework, reducing manual validation effort and accelerating bring-up timelines for multiple networking IP programs.
Collaborated with a distributed cross-geo engineering team (6 engineers) to deliver the networking subsystem on schedule while maintaining high reliability and performance.
Skills:
C, C++, Networking, IPSec, AES, TCP/IP, Low-level Networking, Linux/UNIX, Multithreading, STL, Systems Programming, Python

CC++NetworkingIPSecAESTCP/IP+6

System Validation Engineer

May 2018 – May 2021 · 3 yrs · On-site

Architected an automated platform validation framework for system-level verification of storage, memory, SoC, and power subsystems, simulating production workloads and failure conditions.
Designed and implemented a scalable storage validation platform for NVMe, SATA, and UFS devices, enabling automated execution of I/O performance, stress, endurance, and fault-injection workloads across multiple hardware platforms.
Developed 100+ automated system-level tests covering device functionality, error handling, and performance regressions improving platform reliability and reducing manual validation effort.
Architected a production-grade automated validation system for gaming workloads, covering the full lifecycle from download and launch to long-running execution, fault detection, and observability across 50+ games.
Validated platform reliability using 200+ automated, failure-aware scenarios, enabling scalable regression detection and rapid diagnosis of system-level issues.
Acted as technical lead for a 10-engineer team, owning architecture reviews, execution strategy, and delivery of complex platform projects within schedule and scope.
Drove $100K+ annual cost savings by eliminating manual workflows through backend automation and system-level optimization.
Skills: C++, Linux, Multithreading | Python, Automation | Storage, NVMe, SATA, REST APIs, GIT, Microservice.

C++LinuxMultithreadingPythonAutomationStorage+5

Shoretel

Software Engineer

Feb 2016 – May 2018 · 2 yrs 3 mos · Bengaluru · On-site

Implemented 'call waiting and forwarding' feature for Shoretel Telephony workgroup
solution using C/C++ in a Linux environment.
Participated in defect triage, root cause analysis, and crash dump analysis.
Contributed to project documentation by learning from existing documents and
integrating them into the main project documentation branch.

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