Pratheek J Kumar

Product Engineer

Bengaluru, Karnataka, India1 yr 10 mos experience

Key Highlights

Expert in VLSI Design and Verification.
Proficient in HDL and EDA tools.
Strong background in formal verification methodologies.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI design and formal verification.

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Skills

Core Skills

Formal VerificationDesign Engineering

Other Skills

PCIeHDMIDisplayPorteDP Verification IPsAssertionsCoverage AnalysisJasperGold FPVvManagerIMCsimvisionXceliumC (Programming Language)Digital DesignsCadence SoftwareEDA

About

Passionate about VLSI, with a focus on Design and Verification. Skilled in HDL languages (Verilog), HVL (System Verilog), UVM methodologies(Basics) and EDA tools (Cadence, Mentor Graphics). Dedicated to designing and verifying high-performance, high speed IPs. Excited to connect with professionals in the field and contribute to cutting-edge semiconductor technology. Possess an experience in Formal verification and VIP. Skilled in Checkers, SV Assertions, Functional Coverage, Code Coverage etc

Experience

1 yr 10 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 10 mos

Current Experience

Siemens eda (siemens digital industries software)

Member of Technical Staff

Aug 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

Leading PCIe, HDMI, DisplayPort and eDP Verification IPs support for the customers across APAC.

PCIeHDMIDisplayPorteDP Verification IPsFormal VerificationDesign Engineering

Cadence design systems

Design Engineering Intern

Aug 2023 – Jun 2024 · 10 mos · Bangalore Rural, Karnataka, India · On-site

Completed full formal flow from Test plan creation to Coverage Analysis
Experienced in writing feature specific Assertions and Aux logic
Good understanding of liveness properties, abstraction techniques and blackboxing
Tools Used : JasperGold FPV, vManager, IMC, simvision, Xcelium

Formal VerificationAssertionsCoverage AnalysisJasperGold FPVvManagerIMC+3