Pratik Ashar

Product Manager

Mumbai, Maharashtra, India17 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in compiler design and optimizations.
Significant contributions to Intel Graphics Compiler.
Passionate about enhancing compiler performance.

Stackforce AI infers this person is a Compiler Engineer with expertise in Graphics and Performance Optimization.

Contact

Skills

Core Skills

CompilersLlvm

Other Skills

Code generationOptimizationsDebug information generationVISA code genSPIRV decoderJIT compile timeGraph colouring register allocatorProfilingJava-like VMLoop optimizationsCC++DebuggingProgrammingComputer Science

About

Interested and passionate about compiler design. I’ve experience working in different parts of compiler stack such as: * Code generation, * Generic and target specific optimizations, * Register allocation and spill code cleanup, * Debug information generation. I’ve working experience with open source LLVM compiler toolchain. As a team player, I’ve collaborated in design and implementation of several major features in Intel Graphics Compiler. In addition to developing compiler software, I’ve also worked with architects for path finding. I’m an IRONMAN 70.3 finisher and 140.6 aspirant.

Experience

17 yrs 6 mos

Total Experience

17 yrs 6 mos

Average Tenure

17 yrs 6 mos

Current Experience

Intel corporation

6 roles

Principal Engineer, Compilers

Promoted

Apr 2024 – Present · 2 yrs 2 mos

Graphics Software Engineer

Jun 2013 – Nov 2024 · 11 yrs 5 mos

Part of Intel Graphics Compiler team. The compiler is responsible to generate code for any software targeting Intel’s Gen platform (integrated and discrete).
Designed and implemented several optimisations and passes in code gen:
spill code cleanup,
rematerialization,
local value numbering,
instruction scheduler improvements,
loop discovery, etc.
Implemented stack based calling convention in VISA code gen. Also developed SPIRV decoder for debug information translation and developed DWARF based debug information emission for the stack using LLVM.
Supported various path finding activities by collaborating with hardware architects.
Contributed and collaborated towards IP creation.

Code generationOptimizationsDebug information generationLLVMVISA code genSPIRV decoder+1

Software Engineer

Promoted

Jul 2011 – May 2013 · 1 yr 10 mos

Part of Intel Graphics Compiler team. The compiler targeted Intel’s Gen platform.
Designed and developed local, hybrid RA to improve JIT compile time.
Made several improvements to graph colouring register allocator to handle divergent control flow on GPU.
Improved data structures of compiler based on profiling results.

JIT compile timeGraph colouring register allocatorProfilingCompilers

Software Engineer

Jun 2009 – Jul 2011 · 2 yrs 1 mo

Implemented an O2 level code generator for a well-known Java-like VM targeting x86 platform using proprietary code base.
Designed and implemented several phases in the compiler from scratch:
LIR framework,
peephole optimizations,
linear scan RA
Also implemented several loop optimizations in High Level Optimizer.
Performed extensive profiling of generated code.

Java-like VMCode generationLoop optimizationsCompilers