Pritam Paul

Software Engineer

Bengaluru, Karnataka, India9 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in low power design and power analysis.
Strong background in RTL and gate level optimization.
Passionate about innovative semiconductor solutions.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low power design and power analysis.

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Skills

Core Skills

Low Power DesignSoc DesignPower EstimationPower SignoffRtl Power EstimationPower Aware Design

Other Skills

Software defined vehiclesRadarScriptingPower AnalysisPower DebuggingSynopsys Primtime PXSynopsys Power ReplaySynopsys VerdiVerilogFunctional verificationAXIAHB protocolsUPFUnderstanding of advanced semiconductor packaging technologies25D and 3D integration

About

- SOC & IP level Power Estimation and Optimization - GLS/SDF Based Power Signoff - RTL Power Debugging and improving Clock Gating efficiency - Early Architecture based Power Target/Budgeting - Power Modelling/Analysis/Correlation I have a Master's degree in Electronic Science from Savitribai Phule Pune University. I have also completed multiple certifications in learning Linux command line, UPF power aware design and verification, and attention mechanism. I have a strong background in RTL and gate level optimization, clock-gating, power gating, and other low power design techniques. I am passionate about learning new technologies and skills and applying them to real-world problems. I aspire to contribute to the advancement of the semiconductor industry and the development of innovative and energy-efficient solutions.

Experience

9 yrs 4 mos

Total Experience

2 yrs 11 mos

Average Tenure

7 mos

Current Experience

Marvell technology

Senior Staff Power Design Engineer

Nov 2025 – Present · 7 mos · Bengaluru, Karnataka, India · On-site

Nxp semiconductors

SoC Low Power Engineer

Aug 2022 – Nov 2025 · 3 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Software defined vehiclesRadarLow Power DesignSoC Design

Qualcomm

2 roles

RTL Design Engineer

Jan 2021 – Aug 2022 · 1 yr 7 mos

Senior Engineer

May 2019 – Jan 2021 · 1 yr 8 mos

Part of the Camera team for the mid-tier Snapdragon series of chipsets. I'm responsible for handling the Power aspect of the design. Co-relating RTL based power estimation with the Gate level netlist ptpx data and making sure the chip meets the power budget .
Generating SDF based GLS vectors for early estimation of power using Synopsys Power Replay.
Improving the CGE and DCGE percentage at the RTL level through early power estimation using Ansys PowerArtist.
Finally signing off the power numbers through Primtime PTPX runs.
Skills acquired:-
Scripting, Power Analysis, Power Debugging
Tools used:-
Synopsys Primtime PX, Synopsys Power Replay, Synopsys Verdi

ScriptingPower AnalysisPower DebuggingPower EstimationPower Signoff

Intel corporation

2 roles

Design Engineer

Jan 2018 – May 2019 · 1 yr 4 mos

As a part of the HPG family at Intel, I was involved with Intel first 5G modem chip Polaris or 8060.
Initially as a SOC Design Engineer , I was responsible for handling the RTL power estimation and suggesting Design changes to the RTL team for better Clock gating efficiency and better power aware designs.In this role, i also explored the functional verification aspect of Design and also developed a deep understanding of UPF and its aspects when i explored its use in Power Aware Verification.
Skills acquired:- verilog, Functional verification , AXI, AHB protocols, UPF

VerilogFunctional verificationAXIAHB protocolsUPFRTL Power Estimation+1

Intern

Feb 2017 – Jan 2018 · 11 mos

I started my vlsi career by experiencing the backend side of Semiconductor design cycle. I worked on physical verification of FIVR blocks for Intel's Icelake project. Understanding the ASIC flow and the importance of each stages.Briefly experimenting with Primetime STA and Signal intergrity tools from Synopsys.
Tools - ICC, Design Compiler