Rahul Pattela

Software Engineer

Andhra Pradesh, India8 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in C and SystemVerilog for silicon design.
  • Proven leadership as Senior Lead Engineer at Qualcomm.
  • Strong foundation in ASIC/SoC design verification.
Stackforce AI infers this person is a semiconductor design expert with a focus on verification methodologies.

Contact

LinkedIn

Skills

Core Skills

CSystemverilog

Other Skills

VerilogUniversal Verification Methodology (UVM)axi4PerlShell ScriptingC++

Experience

8 yrs 7 mos
Total Experience
1 yr 11 mos
Average Tenure
8 mos
Current Experience

Qualcomm

Senior Lead Engineer

Oct 2025 – Present · 8 mos · Hyderabad, Telangana, India · On-site

CSystemVerilogVerilogUniversal Verification Methodology (UVM)axi4Perl+2

Amd

Sr. Silicon Design Engineer

Oct 2021 – Oct 2025 · 4 yrs · Hyderabad, Telangana, India

Soctronics

3 roles

Engineer 2

Promoted

Jul 2020 – Oct 2021 · 1 yr 3 mos

Engineer 1

Promoted

Jul 2019 – Jun 2020 · 11 mos

Engineering Trainee

Jul 2018 – Jun 2019 · 11 mos

  • ASIC/SoC Design Verification

Veda iit

Logic Design intern

Jan 2018 – Jun 2018 · 5 mos · Hyderabad, Telangana, India

Microlink peripheral controls pvt ltd

Embedded Trainee

Jun 2013 – Nov 2013 · 5 mos · Vijayawada Area, India

  • 8051 based Embedded systems

Education

Velagapudi Ramakrishna Siddhartha Engineering College

Bachelor of Technology — electronics and communication engineering

Jan 2014 – Jan 2017

Govrnment polytechnic college, vijayawada

Diploma — Electronics and communication engineering

Jan 2011 – Jan 2014

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