Rakesh Mahapatra

Software Engineer

Hyderabad, Telangana, India9 yrs 2 mos experience

AI ML PractitionerAI Enabled

Key Highlights

Expert in RTL design and micro-architecture.
Proficient in FPGA prototyping and hardware validation.
Experienced in advanced-node development flows.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC and FPGA technologies.

Contact

Skills

Core Skills

Fpga PrototypingSoc IntegrationRtl DevelopmentAsic Design

Other Skills

AI/ML acceleration SoCshigh-speed interface IPscustom acceleratorsRISC-V processorsAXI/APB fabricsPCIeDDRperipheral IPson-chip interconnectsfront-end quality flowssynthesis environmentstiming closuremulti-FPGA platformsProtoCompilerSynplify

About

Experienced in designing and integrating complex digital systems involving RISC-V/ARM subsystems, PCIe, AXI interconnects, DDR controllers, and high-speed interfaces across ASIC and multi-FPGA platforms. Skilled in: • RTL design and micro-architecture using Verilog/SystemVerilog • FPGA prototyping and hardware validation • Timing closure, synthesis, and constraint development • SoC integration and low-power design methodologies • Advanced-node development flows (7nm/2nm) • Debug and performance optimization on FPGA hardware platforms Hands-on experience with Vivado, Synplify, ProtoCompiler, Design Compiler, VC SpyGlass, Verdi, and industry-standard ASIC/FPGA development flows. Worked on machine learning acceleration systems, mixed-signal sensor IPs, adaptive clocking architectures, and high-performance compute platforms.

Experience

9 yrs 2 mos

Total Experience

3 yrs 4 mos

Average Tenure

2 yrs 5 mos

Current Experience

Synopsys inc

2 roles

Senior Staff Engineer

May 2026 – Present · 1 mo

Staff Engineer

Jan 2024 – May 2026 · 2 yrs 4 mos

Ceremorphic, inc.

Senior Engineer-II

Oct 2019 – Dec 2023 · 4 yrs 2 mos · Hyderabad

Worked on AI/ML acceleration SoCs and large-scale FPGA prototyping platforms for advanced compute systems.
Led RTL development of high-speed interface IPs including MIPI CSI-2 Rx Controller featuring deskew, descrambling, lane merging, and ECC/CRC handling.
Integrated complex SoC subsystems involving custom accelerators, RISC-V processors, AXI/APB fabrics, PCIe, DDR, and peripheral IPs targeting machine learning acceleration platforms.
Generated and configured on-chip interconnects using ARM Socrates and contributed to front-end quality flows, synthesis environments, and timing closure for TSMC 5nm designs.
Prototyped full SoCs across multi-FPGA platforms using ProtoCompiler and Synplify, including FPGA partitioning, implementation, bitstream generation, hardware bring-up, and system-level debug on proFPGA and HTG platforms.

AI/ML acceleration SoCsFPGA prototypingRTL developmenthigh-speed interface IPsSoC integrationcustom accelerators+17

Sankalp semiconductor

Senior Design Engineer

Feb 2017 – Sep 2019 · 2 yrs 7 mos

Worked on ARM-based SoC integration, clocking architecture, and front-end quality flows for advanced-node ASIC designs. Contributed to 7nm HBM PHY test-chip integration and collaborated closely with synthesis, STA, and backend teams on timing closure and implementation support.

ARM-based SoC integrationclocking architecturefront-end quality flows7nm HBM PHY test-chip integrationtiming closureimplementation support+2