Aug 2022 – Apr 2026 · 3 yrs 8 mos · Bengaluru, Karnataka, India · Hybrid

• High Speed, high accuracy, low power analog circuits designs such as PLL, CDR, LDO, Slicer/Sampler, TRX. Standards such as USB3, eUSB2 and DP. CDR for 60GHz wireless link. Various types of clock generation, distribution and related considerations.

Jun 2020 – Jul 2022 · 2 yrs 1 mo · Lausanne, Vaud, Switzerland

• Design of high frequency clock generation circuits for high speed links.
• Low jitter hybrid PLL, LC VCO, PLL modelling, TX jitter budgeting,
• RX CTLE and other measurements with eye-scope, DFE adaptation DACs, highest speed DIV-by-3, Low jitter Duty-cycle correction, high speed clock routings.

Jan 2019 – May 2020 · 1 yr 4 mos · Neuchâtel, Switzerland · On-site

• 1. Ultra low power and fast startup analog PLL.
• 2. Ultra low power oscillator (FRO) with high temperature stability fast startup.
• 3. Low power energy harvesting receivers. (voltage doubler, low supply ring oscillator, data detection etc.)

Jul 2017 – Dec 2018 · 1 yr 5 mos · Geneva, Geneva, Switzerland

• RF IoT transceiver design at 22nm FDSOI technology
• 1. Receiver front-end: Mixer and TIA
• 2. LC VCO: 3-4 GHz
• 3. Offset LO scheme with Polyphase filter, gilbert cell mixer etc. Multi-modulus divider design.

Jan 2014 – Jun 2017 · 3 yrs 5 mos · Switzerland

• Clock generation circuits: Design/Improvement, simulation, layout and measurement of clock generation circuits such as TDC, divider, DCO for a ADPLL, low power ring oscillator, low jitter REF clock buffer, novel low mismatch divider, active mixer for frequency addition for wireless applications such as NFC/BT/WLAN etc. in 28nm and 40nm CMOS technologies. Performance achieved are at the state of the art or better. System level understanding of Bluetooth and Wifi MIMO transceivers. On chip 8-shape inductor design. LO distribution repeater design for MIMO transceivers. Distortion cancellation utilizing multiple phases consuming very low extra power.

Mar 2009 – Dec 2013 · 4 yrs 9 mos · Greater Enschede Area

• Ultra Low power and interference robust wireless transceiver techniques for wireless sensor networks.
• 1. Ultra low power receiver: System analysis, architectural optimization, designed circuit blocks, PCB design and rigorous measurement. Receiver energy per bit achieved 3 times lower than the state of the art. Key low power techniques:
• a. A novel 3-phase voltage-mode passive mixer with combination of L-match and 3 stage ring digital controlled oscillator.
• b. Mixer-first direct conversion architecture in combination with BFSK modulation and optimized choice of datarate and noise figure.
• c. Frequency correction loop (faster correction and duty-cycled to save power) instead of PLL.
• d. A novel ultra low power BFSK demodulator circuit.
• 2. Chirped-LO scheme proposed, simulated and measured to IC to prove interference robustness even at ultra low power (13/14 dB better).
• 3. System level trade-offs to reduce energy consumption of a duty-cycled transceiver.
• 4. Compared by analysis and simulation divider mismatch for a given power, which shows promising advantage of dynamic transmission gate logic over CML at advance technology node and in moderate frequency range.

Aug 2008 – Feb 2009 · 6 mos · bangalore

• Digital to Analog Converters - feasibility study and modeling. Architectural trade-off for lower power consumption and area for a 12 bit segmented current steering D/A converter.

Jan 2006 – Jul 2008 · 2 yrs 6 mos · Kharagpur

• 1. Low mismatch and power consumption multi-phase clock generation: compared various dividers/shift register type multiphase generator for low power, mismatch and noise.
• 2. Proposed a low power architecture to extend the tuning range of a quadrature clock.
• 3. Low mismatch clock buffer: Derived optimum inverter stage ratio to minimize power and mismatch FoM.
• 4. Design and layout of a 18mW 4 bit 1.6GSPS flash A/D converter in 180nm CMOS.

Jul 2002 – Jan 2006 · 3 yrs 6 mos · Bangalore

• High Density and Low power SRAM design, IO and Mixed signal circuits. Design/development of Low delay rail-to-rail comparator, bandgap reference, current references, offchip drivers, address decoder, low power delay cells, JTAG methodology, ESD improvement etc.