Sai Teja Gorantla — DevOps Engineer
◦STA/Full Chip Timing - Handled Timing Closure and related activities of high frequency designs at both chip and block level at below 5 nm tech nodes. - Well versed with debugging and resolving violations for Timing Convergence in various Modes and Corners [DMSA]. - Have great understanding of clock architecture and deep sub-micron design issues such as cross talk, ocv, aocv, pocv etc. - Familiar in collaborating with design, DFT and PD teams and resolve issues w.r.t constraints, STA, Physical design, etc. - Worked on generating Timing ECOs for various violations including setup, hold, trans etc. - Custom Scripting in PT— Cell swapping for violations, Clock Network cell segregation, Skew analysis of paths etc. ◦ Synthesis - Executed and Owned Synthesis & Power Aware Synthesis with Fusion Compiler for all the blocks of an IP. - Very well versed with Optimization techniques w.r.t Timing, Area and nuances related to QoR to achieve target PPA. - Have impeccable knack of intricacies and understanding of Timing Paths to accomplish Timing Closure. - Very well versed with Fusion Compiler shell in custom scripting, analysis and debug of various violations. - Owned Full chip-level Synthesis & Physical Synthesis which include UPF, MBIST, SCAN Insertion. - Familiar with execution of Top-Down (Flat) & Bottom-Up (Hierarchical) and handling various optimization strategies for better QoR. - Familiar with writing Functional netlist ECOs based on the bugs identified in RTL. ◦ Constraints - Owned Constraints, well versed with defining Clocks, inter-clock relations etc. according to the clock tree structure. - Handled Exceptions and IO budgeting for resolving numerous categories of violations for Timing Signoff. - Familiar with GCA for checking constraints consistency with design and fixing corresponding errors/warnings. ◦ Formal Equivalence - Handled Formality for RTL2Gates, Gates2Gates including UPF, familiar with debugging Failing and Abort points. ◦ Power - Familiar with Power and its related activities such as PTPX, power calculation and debug etc. ◦ Vclp & Conformal Equivalence - Familiar with Synopsys VCLP & Cadence Low-Power (CLP-Verify) for checking UPF consistency with RTL and Netlist. - Performed low power equivalence check (LP-EC) for RTL2gates and gates2gates including UPF. - Familiar with generating Functional ECOs using Conformal ECO to be used in PnR implementation. Tools: Prime Time (PT), Design Compiler, Fusion Compiler, Formality, Conformal (Low Power Equivalence, ECO), ICC2, VCLP*, GCA Others: Perforce, Git, Vim, Linux
Stackforce AI infers this person is a Semiconductor and Image Processing specialist with a focus on ASIC design.
Location: Hyderabad, Telangana, India
Experience: 10 yrs
Skills
- Timing Closure
- Synthesis
- Image Processing
Career Highlights
- Expert in Timing Closure for advanced chip designs.
- Proficient in Synthesis and Power Aware Synthesis techniques.
- Strong background in Image Processing and Algorithm Design.
Work Experience
Qualcomm
Senior Lead Engineer (1 yr 1 mo)
AMD
Senior Silicon Design Engineer (3 yrs 11 mos)
Samsung Electronics
Senior Design Engineer (2 yrs 11 mos)
Summer Intern (2 mos)
Prof. Tanaya Guha, Computer Vision Lab, IIT Kanpur
Red-Eye Correction (4 mos)
Pipelined Image Auto Enhancement (4 mos)
Prof. Ramprasad Potluri, Control Systems Lab, IIT Kanpur
Four Wheel Steering Four Wheel Drive Electric Vehicle (2 mos)
Techkriti, Indian Institute of Technology Kanpur
Senior PR Executive (5 mos)
Antaragni IIT Kanpur
Events Secretary (4 mos)
Counselling Service, IIT Kanpur
Academic Mentor (1 yr 9 mos)
Udghosh, IIT Kanpur
PR Executive (4 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Technology, Kanpur
