Santhan Kumar

Software Engineer

India9 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in VLSI and Embedded Systems
Proficient in Verilog and SystemVerilog
Experience in low power design for video codecs

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and low power systems.

Contact

Skills

Core Skills

VerilogEmbedded SystemsSoc Design

Other Skills

Aldec Riviera-PROAssembly LanguageCadence GenusCadence HAL toolsData StructuresFPGA prototypingLabVIEWLinux (Ubuntu 10.04+)MatlabProgrammingResearchVLSIWindows XP/7/8/8.1Xilinx Vivado

About

Intend to build a career with leading corporate of hi-tech environment with committed and dedicated people to utilize my skills and abilities to become a successful professional in the field of Semiconductor and to work in an innovative and competitive world, which will help me to explore myself fully and realize my potential. Acquired good knowledge and understanding of subjects like ✓ Digital System Design and Static Timing Analysis, VLSI Design and Computer architecture, Microprocessors and Micro Controllers, Embedded Systems and RTOS, Advanced Digital Signal Processing. ✓ verilog HDL, System verilog, VHDL, C, CPP, Python,Perl and Assembly Languages. ✓ Linux/ Windows Operating Systems. ✓ Proficiency at grasping new technical concepts quickly & utilizing it in productive manner. ✓ Possess strong management, communication & interpersonal skills.

Experience

9 yrs 10 mos

Total Experience

2 yrs 5 mos

Average Tenure

4 yrs 4 mos

Current Experience

Amd

RTL Design Engineer

Feb 2022 – Present · 4 yrs 4 mos · Hyderabad, Telangana, India

Xilinx

RTL Design Engineer

Nov 2017 – Feb 2022 · 4 yrs 3 mos · Hyderabad Area, India

Mindlance india

RTL Designer

Jan 2017 – Nov 2017 · 10 mos · Bangalore

Implementation of I2C slave Protocol for 128x8bits-Memory Module supports Auto Increment (Mindlance).
(Implementation of SMBus and PMBus)
EDA Tool : Cadence Genus, Cadence HAL tools (LINT), Aldec Riviera-PRO, ALINT-PRO
Language : Verilog
DESCRIPTION:
Compatible with NXP I2C standard.
Serial, 8-bit oriented, and can support Standard mode and Fast Mode.
Supports 128x8 bits Memory Read/Write.
Supports Repeated Start and Auto Increment.
Supports up to 127 Slave devices.
The implementation is verified with different test cases. LINT checking is done using Cadence HAL and Synthesis using Cadence Genus tools.
Implementation of APB Protocol for 128x32bits-Memory Module (Mindlance).
EDA Tool : Cadence Genus, Cadence HAL tools (LINT), Aldec Riviera-PRO, ALINT-PRO
Language : Verilog
DESCRIPTION:
Compatible with AMBA APB Protocol v2.0.
The implementation is for PMBus slave to read and write different commands from/to external ports, and the synchronization is maintained using Asynchronous FIFO. The implementation is verified with different test cases. LINT checking is done using Cadence HAL and Synthesis using Cadence Genus tools.

VerilogCadence GenusCadence HAL toolsAldec Riviera-PROEmbedded Systems

Clairvolex knowledge processes pvt ltd

IP Engineer

Jul 2016 – Dec 2016 · 5 mos · Gurgaon, India

Rci (drdo)

SOC Designer

May 2015 – Jul 2016 · 1 yr 2 mos · Hyderabad Area, India

A LOW POWER DESIGN OF MOTION ESTIMATION BLOCK IN H.264 VIDEO CODEC Main Project (M. Tech): (DRDO Project-Internship)
EDA Tool : Xilinx Vivado
Language :Verilog
FPGA Board : ZYNQ-7 ZC702 evaluation board
DESCRIPTION: In H.264 Video Codec, Motion Estimation (ME) is critical block which consumes more than 50% of the total power consumed by the Video Codec. In this work, ME block is designed for reducing power consumption using low power Global Elimination Algorithm (GEA). Verilog HDL is used for the hardware design of the ME block. In next phase, RTL low power techniques like clock gating is applied to reduce the power consumption of the ME block in H.264 Video Codec. The design was implemented on ZYNQ ZC702 board. The simulation results and power reports were observed.

VerilogXilinx VivadoSOC Design