Saurav Gupta

Product Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience

Highly Stable

Key Highlights

Over 8 years of experience in hardware accelerator design.
Expertise in computer vision applications and hardware architecture.
Strong background in semiconductor engineering and RTL design.

Stackforce AI infers this person is a Semiconductor Engineer specializing in hardware design and computer vision applications.

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Skills

Core Skills

Hardware ArchitectureComputer VisionFunctional ModelingCamera PerformanceImage Signal ProcessingMultimedia DesignDigital ProcessingModem DevelopmentIntegrationSoc Design

Other Skills

System ArchitectureOpenCVSemiconductor EngineeringCSystem VerilogHW DesignMachine VisionAlgorithm DesignDigital Image ProcessingAlgorithm DevelopmentSystem on a Chip (SoC)DebuggingVHDLVery-Large-Scale Integration (VLSI)Deep Learning

About

I specialize in designing hardware accelerators. I am a Systems Engineer for the Computer Vision Processor in Qualcomm's EVA Systems team. I focus on developing hardware architecture for feature extractors used in various CV use cases like Motion Estimation, Object Tracking etc I work both as an individual contributor as well as a technical lead and have more than 8 years of experience. My background includes roles as a Systems Performance Engineer and RTL Designer for Camera ISP. I am adept in Hardware Systems Design, Functional Modelling, FPGA Implementation, Hardware Programming Languages such as Verilog and VHDL, and High-Level Synthesis (HLS). Let's talk if you're interested in discussing or building power-efficient hardware accelerators or hardware design in general.

Experience

8 yrs 8 mos

Total Experience

2 yrs 9 mos

Average Tenure

8 mos

Current Experience

Hft firm

FPGA Engineer

Oct 2025 – Present · 8 mos

Qualcomm

3 roles

Senior Lead Engineer

Promoted

Dec 2022 – Mar 2026 · 3 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

Systems Engineer - Engine for Visual Analytics (EVA) Hardware
In my role as a Systems Engineer for EVA at Qualcomm, I focus on developing hardware accelerators for computer vision applications, particularly feature extractors. My key responsibilities include:
1. Exploring and evaluating computer vision algorithms for extended reality (AR, VR), mobile, and automotive applications.
2. Designing and architecting hardware systems to support these algorithms.
3. Creating bit exact functional models of computer vision algorithms to be implemented in hardware.
4. Collaborating with design verification (DV) teams, hardware designers, and performance specialists to deliver low-power, high-performance chipsets.

System ArchitectureOpenCVHardware ArchitectureComputer Vision

Senior Engineer

Jun 2022 – Nov 2022 · 5 mos · Bengaluru, Karnataka, India · Hybrid

XR R&D Team
Computer Vision Algorithms for XR Application
Functional Modeling for CV algorithms (to be Hardened)

OpenCVSemiconductor EngineeringComputer VisionFunctional Modeling

Senior Engineer

Jul 2020 – May 2022 · 1 yr 10 mos · Bengaluru, Karnataka, India · Hybrid

Camera Performance - Spectra ISP
As part of the Spectra ISP team, I contributed to enhancing camera performance for Qualcomm Snapdragon SoCs. My key responsibilities included:
1. Analyzing and optimizing camera performance for Snapdragon System-on-Chips (SoCs).
2. Developing performance models for camera Image Signal Processors (ISPs).
3. Creating comprehensive performance test plans for both pre-silicon and post-silicon verification stages.

Semiconductor EngineeringCCamera PerformanceImage Signal Processing

Samsung electronics

2 roles

Associate Staff Engineer

Mar 2020 – Jul 2020 · 4 mos · On-site

Multimedia Design Team
In my role within the Multimedia Design Team, I was responsible for the development and integration of advanced multimedia components for Samsung Exynos SoCs.
Key tasks and responsibilities involved:
1. Developing digital color processing IPs.
2. RTL coding using SystemVerilog and High-Level Synthesis (HLS).
3. Integrating Multimedia blocks in the SoC.
4. Debugging and resolving sanity issues, including DRC checks like CDC and lint.
5. Performing synthesis, Design for Test (DFT), and Unified Power Format (UPF) tasks for multimedia blocks.

Semiconductor EngineeringSystem VerilogMultimedia DesignDigital Processing

Senior Engineer

May 2018 – Mar 2020 · 1 yr 10 mos · On-site

Modem Development Team
As a member of the Modem Development Team, I contributed to the development and integration of modem blocks for Samsung Exynos SoCs.
Key tasks and responsibilities included:
1. Developing compression IPs for modems.
2. Integrating modem blocks in the SoCs.
3. RTL design using SystemVerilog.
4. Collaborating with the design verification (DV) team to review test plans and coverage

Semiconductor EngineeringSystem VerilogModem DevelopmentIntegration