sharath A — Software Engineer
I have completed my DFT course at ChipEdge Technologies, actively seeking job opportunity in Design for Testability. I have been trained with Synopsys tools for Scan Insertion, Scan insertion with Compression, Boundary Scan (JTAG), ATPG Pattern Generation and Simulation.
Stackforce AI infers this person is a DFT Engineer with a focus on Design for Testability in the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 1 mo
Career Highlights
- Trained in Design for Testability at ChipEdge Technologies.
- Experienced in Synopsys tools for DFT processes.
- Strong background in project engineering and management.
Work Experience
Techsoc Technologies Private Limited
DFT Engineer (4 yrs 1 mo)
trineee
DFT Engineer (1 yr 7 mos)
ChipEdge Technologies Pvt Ltd
DFT Engineer (4 mos)
Trainee (3 mos)
G4S
Project Engineer (4 yrs 10 mos)
Project Engineer (4 yrs 9 mos)
ADARSH DEVELOPERS
site enginer electrical (11 mos)
systems
business (8 yrs 8 mos)
Education
Bachelor of Engineering - BE at Visvesvaraya Technological University, Belgaum
school at sri bheemeshwara bala vikas higer primary school