SHARATH S V

Software Engineer

Bangalore Rural, Karnataka, India1 yr 9 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Expert in AMS verification of high-speed SerDes IPs.
Proficient in mixed-signal verification and debugging.
Recognized for contributions to EDA tool validation.

Stackforce AI infers this person is a skilled engineer in the EDA and semiconductor industry.

Contact

Skills

Core Skills

EdaDigital DesignsMachine Learning

Other Skills

Tcl-TkVery-Large-Scale Integration (VLSI)Deep LearningVerilog-AMSDesign FlowGNU MakePerlTkAnalog SemiconductorsDevice Driversx86 AssemblySoftware IntegrationRegression TestingTest AutomationComputer Science

About

Verification Engineer with 1.5 years of experience in AMS Verification of high-speed SerDes IPs, specializing in top-level block verification, mixed-signal verification setup, and debugging. Skilled in verifying PCIe, Ethernet, CPRI, and JESD protocols, developing analog testbenches, and ensuring robust mixed-signal verification flows. Strong expertise in TX/RX datapath, supervisor blocks (rtune, mpll), substate power verification across lanes and sup blocks, and power state validation. Experienced in analyzing digital and analog power consumption, preparing deliverables, and maintaining clean simulation environments for accurate verification sign-off

Experience

1 yr 9 mos

Total Experience

1 yr 9 mos

Average Tenure

1 yr 9 mos

Current Experience

Synopsys inc

ASIC digital design engineer

Sep 2024 – Present · 1 yr 9 mos · Bengaluru South, Karnataka, India · On-site

Proteantecs

EDA solution Intern , R&D

Jan 2024 – Sep 2024 · 8 mos · Bengaluru South, Karnataka, India · On-site

At my current internship with ProteanTecs Ltd., an EDA R&D company, I have been contributing to the validation of the company's PTDM (Proteus Data Model) flow. Highlights of my work include:
Recognition award for my contributions to validating the PTDM flow
Unit testing and basic debugging of ongoing tool and flow developments
Loading design sessions at various stages using industry-standard EDA tools like DC, Genus, Innovus for compilation, debug, and bug reporting
Comparing and debugging reasons for fan-in-cone differences in sequential paths between tool versions using automation scripts
Writing regression test cases for in-house tools, including loading designs, setting options, performing operations, and compiling results using scripts
Circuit simulation using SimTool, gaining experience in validating circuit performance across various PVT corners and Monte Carlo simulations

EDATcl-Tk