S

Sharmila M.

DevOps Engineer

Andhra Pradesh, India2 yrs 1 mo experience
Most Likely To Switch

Key Highlights

  • Experienced in Digital Design and Verification.
  • Proficient in Universal Verification Methodology (UVM).
  • Mentored VLSI aspirants in frontend design and verification.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital design and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogDigital ElectronicsVerilogHtmlCascading Style Sheets (css)

Other Skills

AngularJSCore JavaJavaScriptAmazon Web Services (AWS)QuestaSimLinuxAMBAAXIEtherNet/IPSystem Verilog AssertionsAMBA AHBFunctional VerificationcodecoverageFunctional coverageLinting

Experience

2 yrs 1 mo
Total Experience
1 yr
Average Tenure
1 yr 10 mos
Current Experience

Smartsoc solutions pvt ltd

Design Verification Engineer

Aug 2024 – Present · 1 yr 10 mos · Hyderabad · On-site

Universal Verification Methodology (UVM)SystemVerilog

Maven silicon

2 roles

Project Intern

Jul 2023 – Oct 2023 · 3 mos · Bangalore Urban, Karnataka, India · On-site

  • Worked on developing AMBA protocols.
  • Mentoring VLSI aspirants in frontend Design and Verifcation.
Digital ElectronicsVerilog

Advanced VLSI Design and Verification

Oct 2022 – Jun 2023 · 8 mos · Bangalore Urban, Karnataka, India · On-site

Digital ElectronicsVerilog

Wipro

Project Engineering Intern

Apr 2022 – Jun 2022 · 2 mos

HTMLCascading Style Sheets (CSS)

Education

JNTU Gurajada Vizianagaram

Bachelor of Technology - Electronics and Communication Engineering

Jan 2019 – Jan 2022

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