Sirsha Das — Product Manager

Experienced on SOC Design Verification using UVM and Perl.Working with AMD as. SOC Design Verification Engineer Intern. Advance Micro Devices (AMD) 👉 worked with AMD as an INTERN. 👉 worked on company specific tools 👉 worked on various software and Hardware language sich as VERILOG,SYSTEM VERILOG,UVM, Perl,C++. 👉 I am working on JTAG and AXI protocol. 👉I worked on a inhouse prohect YAPP Router in UVM MTECH DEGREE 👉 I completed my post graduation from VELLORE INSTITUTE OF TECHNOLOGY in VLSI deaign Engineering. 👉I have knowledge of CAD,Testing,ASIC Design, SOC Design, CMOS Technology,STA,ASIC design, POWER/CLOCK Gating technique. 👉 I studied VERILOG,SYSTEM VERILOG, UVM,LINUX. 👉I worked on Cadence tool for physical Layout. 👉 worked on two project on SRAM design for low power consumption using JLTFET. Implemented the Deaign using CADENCE tool 👉For the second project worked on SYNOPSYS TCAD to design the JLTFET to DESIGN THE SRAM. 👉 I published one paper on IEEE conference 👉I completed My BTECH degree from SILIGURI INSTITUTE OF TECHNOLOGY in ELECTRONICS and COMMUNICATION ENGINEERING. 👉 In BTECH I ave knowledge of the basics electronics, digital electronics and the mid level with scripting Language. 👉As GENPACT is my first company I learnt about work life culture, team bonding. 👉I worked on Perl, linux.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in digital design and verification.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 10 mos