Sirsha Das

Product Manager

Bengaluru, Karnataka, India6 yrs 10 mos experience

Key Highlights

  • Strong foundation in VLSI design and verification.
  • Hands-on experience with DFT and UVM methodologies.
  • Published research at an IEEE conference.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in digital design and verification.

Contact

Skills

Core Skills

DftAtpgUvmLogic DesignVlsi DesignDigital Electronics

Other Skills

Universal Verification Methodology (UVM)CadenceGuaranteesIjtagEDTOCCScan InsertionObject-Oriented Programming (OOP)TCLCAD ToolsStatic Timing AnalysisConsumer ElectronicsProgrammingElectronic CircuitsMicroprocessors

About

Experienced on SOC Design Verification using UVM and Perl.Working with AMD as. SOC Design Verification Engineer Intern. Advance Micro Devices (AMD) πŸ‘‰ worked with AMD as an INTERN. πŸ‘‰ worked on company specific tools πŸ‘‰ worked on various software and Hardware language sich as VERILOG,SYSTEM VERILOG,UVM, Perl,C++. πŸ‘‰ I am working on JTAG and AXI protocol. πŸ‘‰I worked on a inhouse prohect YAPP Router in UVM MTECH DEGREE πŸ‘‰ I completed my post graduation from VELLORE INSTITUTE OF TECHNOLOGY in VLSI deaign Engineering. πŸ‘‰I have knowledge of CAD,Testing,ASIC Design, SOC Design, CMOS Technology,STA,ASIC design, POWER/CLOCK Gating technique. πŸ‘‰ I studied VERILOG,SYSTEM VERILOG, UVM,LINUX. πŸ‘‰I worked on Cadence tool for physical Layout. πŸ‘‰ worked on two project on SRAM design for low power consumption using JLTFET. Implemented the Deaign using CADENCE tool πŸ‘‰For the second project worked on SYNOPSYS TCAD to design the JLTFET to DESIGN THE SRAM. πŸ‘‰ I published one paper on IEEE conference πŸ‘‰I completed My BTECH degree from SILIGURI INSTITUTE OF TECHNOLOGY in ELECTRONICS and COMMUNICATION ENGINEERING. πŸ‘‰ In BTECH I ave knowledge of the basics electronics, digital electronics and the mid level with scripting Language. πŸ‘‰As GENPACT is my first company I learnt about work life culture, team bonding. πŸ‘‰I worked on Perl, linux.

Experience

6 yrs 10 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Mediatek

DFT Engineer

Jul 2024 – Present Β· 1 yr 11 mos Β· Bengaluru, Karnataka, India Β· On-site

  • I am working as a DFT design Engineer.
  • with Mediatek I am working on ATPG tasks. coverage analysis, simulations, TTSC, DFTV check.
  • ● I have worked on coverage improvement and improved the coverage.
  • ● I have worked on Simulation stuck at fault and transition simulations
  • ● I have checked on the TTSC
  • ● I performed DFTV check for the project
ATPGDFT

Amd

2 roles

Engineer Intern

Aug 2022 – Aug 2023 Β· 1 yr Β· Bengaluru, Karnataka, India

  • I am working with Advance Micro Devices as an Intern. I worked on various project related to DFT and DV and developes various skills related to project as well as the team bonding skill.
Logic DesignUniversal Verification Methodology (UVM)UVM

Design Verification Engineer

Aug 2022 – Aug 2023 Β· 1 yr Β· Bengaluru, Karnataka, India

Vellore institute of technology

Masters Student

Aug 2021 – Jul 2023 Β· 1 yr 11 mos Β· Chennai, Tamil Nadu, India

  • I was a student of VLSI design. I learnt verious skills. System verilog,Verilog, UVM,Testing, Clock Gating,Power gating,STA, RTL design, Memory devices, SOC, ASIC
CadenceLogic DesignVLSI Design

Genpact

Process System Engineer

Sep 2018 – Aug 2021 Β· 2 yrs 11 mos Β· Hyderabad, Telangana, India Β· On-site

  • I was working in GENOACT PVT. LTD. as a process System Engineer.
Digital ElectronicsGuarantees

Education

Vellore Institute of Technology

Master's degree β€” VLSI

Aug 2021 – Jun 2023

Siliguri Institute of Technology

Bachelor of Technology - BTech

Jan 2014 – Jan 2018

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