Sneha Raghunath — Product Manager
Currently contributing as AMS Verification, Lead Design Engineer at Cadence, focusing on the verification of analog mixed-signal blocks such as Soundwire, eUSB2v2 PHY, and die-to-die interconnects for TSMC and Intel advanced nodes. Proficient in creating behavioral models (BMODs) and validating them with a self-level testbench to ensure system performance and reliability. Skilled in TCL, Perl, and Liberty, with experience working across leading technologies.
Stackforce AI infers this person is a Semiconductor Verification Specialist with expertise in analog mixed-signal design.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Analog Mixed-signal Verification
- Behavioral Modeling
- Circuit Design
- Characterization
- Static Timing Analysis
- Asic Verification
Career Highlights
- Expert in analog mixed-signal verification.
- Proficient in behavioral modeling and testbench validation.
- Experienced in cutting-edge semiconductor technologies.
Work Experience
Cadence
AMS Verification, Lead Design Engineer (1 yr 7 mos)
Synopsys Inc
A&MS Circuit Design Sr Engineer (2 yrs 11 mos)
A&MS Circuit Design Engineer I (3 yrs 1 mo)
Engineering Contractor (3 mos)
PinE Training Academy
Trainee (10 mos)
Education
Bachelor's degree at Raj Kumar Goel Institute of Technology, Ghaziabad
Higher secondary Education at St Joseph's Academy
High School Education at St Joseph's Academy, Savita Vihar
