Jul 2024 – Nov 2025 · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

• Member of Dell Core BIOS Team.
• Providing support for Qualcomm Hamoa Chipset integrated Laptop.

May 2022 – Jun 2024 · 2 yrs 1 mo

•  Support for DHCP, NTPin Multi Chassis and Intra NE.
•  Support for Infinera G4X/G3X series switches QEMU based simultaor bring-up and x86 virtualization using qcow2 image.
•  Support for Syslog-ng and wrapper logging service.
•  Support for Docker based build environment and container support for deploying 3rd party applications.
•  Support for OOPS,kernel panic logging, Kdump tool,kernel patches and kernel builds for Ls1046 processor.
•  Support for crosstool-ng support and cross compilation in ARM/X86 based build.
•  Design and development for Hitless Software Upgarde/ISSU, Frimware Upgrade,Delta Upgrade
•  Design High Availability,Fault tolerant System with 99.99% availability.
•  Support for Firmware Security and SW Security.
•  DDR support with changes in RCW file for PBL., DDR eeprom and temp Sensor support via I2c. DDR memory testing support via Memtester tool.
•  Support for Board Bring Up of x86(Denverton from Intel) and NXP LS1046 Processor(Arm Based) using PBL, UBoot, ONIE, ONL Kernel, device driver and device tree based configuration.
•  Support for UART and baud rate changes on system.
•  Support for SW Installation and Management using GRUB and uboot env variable in SSD.
•  Support for SSD stress testing and characterization using iozone.
•  Fan control algoritm, Power Management, Thermal Testing Support to EDVT team for DDR4 DIMM Sensor, BCM PCIE Sensor, Gecko Sensor, Alaska Sensor, FPGA(Tmp435) and CPU Sensors(Tmp435)

Feb 2017 – May 2022 · 5 yrs 3 mos

Dec 2013 – Feb 2017 · 3 yrs 2 mos · Bangalore

•  Development of Running Config Framework in ME1200 (Sandino) Box using Soap protocol.
• Protocol: SOAP
•  Design, Development, coding and Implementation of port based licensing model of ASR920 series of switches.
• Developed port based license model for 1G and 10G port, depending on customer requirement.
• Dual rate port based license model depends on customer requirement.
•  Development of SNMP support for ASR920 , ASR903 and ME3600 series of switches.
• Development of alarm generation procedure of different on board sensors present.
• Development of SNMP query on different counters i.e unicast , multicast, broadcast of an Ethernet interfaces.
• Development of trap in agent(switch) on insertion of FRU and config change.
• Protocol : SNMP
• Responsible for development of Crete platform. (12x1G + 4x10G ) switch.
• .Responsible for Handoff FPGA(master) Programming via SPI Flash(slave) via SPI protocol. There are two images in the SPI-Flash, a golden image and an upgrade image. Crete supports field upgrade of the upgrade image. Detail how the FPGA chooses the running image is given in the Xilinx FPGA specification document. In summary, the boot vector in the golden image instructs the FPGA to try the upgrade image and starts the fallback timer. If the upgrade region is blank or bad, the fallback time expires, and the FPGA goes back to the golden image.

Feb 2011 – Nov 2013 · 2 yrs 9 mos · Bangalore

•  Responsible for development on ME3600, ME3800, ME3600-CX and ASR921 series of high end switches.
• Development support for optical transceiver (XFP, SFP and SFP+) on ME3600 series of switches.
• Worked on SFF8472 standard which implements Diagnostic Monitoring Interface for Optical Transceivers.
• Worked on SFF8477 which implements Tunable XFP for ITU Frequency Grid Application.
• Worked on SFF8089 which implements SFP rate and application code.
• Worked on SFF8431 which implements Enhanced Small Form Factor pluggable module SFP+.
• Worked on INF8074 which implements SFP Transceiver.
• Protocol : I2C
•  Development support for Software upgradation from one release to another release.
• Design of the download procedure, coding and implementation.
• Control FPGA Programming, Plankton devices programming and On board FPGA Programming, Wintegra Processor eeprom programming.
• Protocol: I2C, SPI
•  Development support for operation in WAN mode for Vittese8487(10G) phy in ME3600-CX box.
• Support for operating in WAN mode for 10G vittese phy.
• Protocol: MDC/MDIO
•  Design, Development, Coding and Implementation of Front Port Disabling feature for ASR920 series(Pegasus 1M board)
• This board having 1 insertable module . As asic can’t support both of them together, front port(8x1G) has to be disabled or enabled on request.

Jun 2010 – Feb 2011 · 8 mos · Bangalore

• 1.Implementation of statistic service in middleware of ENIP core package in a network following distributed kernel architecture.
• 2. Worked as a designer in statistics module development which is a part of the mobile billing system used by customer of Huawei. It is a high performance cpu critical application.

Jun 2006 – Apr 2010 · 3 yrs 10 mos · Bengaluru Area, India

• Worked in Diagnostic software development for TJ1270 series of cards.
• 1. Implementation of datapath testing of VC-12 and VC-4 granularity level in a STM-1 base card(TJ1270) with help of FPGA. Worked as a designer in implementing cross connect using FPGA module and integration check of the path covered by the Base card to trib card.
• 2. SDflash Testing: Implementation of SD card testing using Max Algorithm. This involves address bus, data bus, data retention, data equal address, data not equal to address and random data pattern test.
• 3. Eeprom Access: Implementation of eeprom access with help of I2C Protocol.
• 4. RTC Access: Implementation of RTC Access using I2C Protocol.