Subrata Roy

Director of Engineering

Bengaluru, Karnataka, India25 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 20 years of EDA/CAD tool development experience.
Expertise in DFT tools and automation.
Proven leadership in managing cross-functional teams.

Stackforce AI infers this person is a seasoned expert in EDA/CAD tools with a strong focus on DFT and automation.

Contact

Skills

Core Skills

EdaDftC++HdlFpga

Other Skills

DFT Insertion ToolsDFT CAD toolsPower Insertion toolsDesignImplementationDocumentationRegression testingSystem testingDFT features identificationDFT flows developmentUser interactionProject trackingBug fixingHierarchical Netlist databaseWGL parser

About

Experience : 20+ years of EDA/CAD Tool Development, Scripting and Testing Experience. Designation : Sr. CAD Manager. Software skills : C, C++, Perl, Unix, XML, PHP, OOPS, OOAD. Technology Skills : EDA, CAD, DFT tools, Scan Insertion, Logic Synthesis, Power Insertion, Netlist Parser, Tool Automation. 1. Experience of managing team. 2. Software Tools Development 3. Developed many tools using C and C++ in Linux Environment. 4. Developed few automated tools using Perl/Php in Linux Platform. 5. Involved in complete software development and testing life cycle. 6. Worked in development and maintenance of EDA Tools, HDL Synthesis, Package Pin Assignment, Hardware Simulation, Verification Specialties : C, C++, Unix, Perl, EDA, DFT

Experience

25 yrs 1 mo

Total Experience

8 yrs 4 mos

Average Tenure

15 yrs 6 mos

Current Experience

Nvidia

3 roles

Director

Promoted

Mar 2026 – Present · 3 mos

Sr CAD Manager

Oct 2014 – Mar 2026 · 11 yrs 5 mos

Developing DFT Insertion Tools.

DFT Insertion ToolsEDADFT

Sr CAD Engineer

Nov 2010 – Sep 2014 · 3 yrs 10 mos

In NVIDIA I am developing DFT CAD tools for Scan Chain Insertion.
I also develop Power Insertion tools, i.e Clamp Insertion/Level Shifter Insertion.
My responsibility includes
1. Design, Implementation,documentation, regression and system testing.
2. Identification of new DFT features.
3. Development of different kinds of DFT flows.
4. Interacting with user DFT team and resolving issues.
5. Project tracking and Bug fixing.
5. Making sure all the chip passes through DFT flow smoothly.
6. Helping other team members.

DFT CAD toolsPower Insertion toolsDesignImplementationDocumentationRegression testing+8

Kawasaki micro electronics

Tech Lead

May 2007 – Nov 2010 · 3 yrs 6 mos

1. Developed Hierarchical Netlist database using C++. Netlist is gate level representation of a CHIP. A real CHIP contains multi million Gates. Netlist database composed of objects/classes for Net, Assignment, module, instance, port and terminal. All the objects are hierarchically connected to represent netlist database.
2. Developing WGL parser and post processing of WGL data using c++ in Unix.
3. Developed Liberty Parser and Characterization Tool. I have developed Liberty parser interface for synopsys c++ Liberty parser. Every element in the database is editable by Tcl Interface and using string interface. Did complete testing and automation of testing process.
I have developed Characterization tool to generate library file by using C++ parser APIs. This tool reads many text data from pin database and populates delay information in the library to be written.
4. Developing Design Flow using Perl/Tcl.
5. I have developed Error Handing System, Resource Management System.
6. Also web development using MyQSL/PHP.
7. My other responsibility include managing team, code reviews e.t.c

Hierarchical Netlist databaseWGL parserLiberty ParserCharacterization ToolDesign FlowError Handling System+4

Softjin technologies

Project Leader

Apr 2001 – May 2007 · 6 yrs 1 mo · Bangalore

1. HDL synthesis Tool.
I was involved in the development of a light weight synthesis tool for Verilog and VHDL.
The current project is to enhance the capability of GATE-level equivalence checker, so that it can do RTL-level equivalence checking. It has been developed on CDFG database. And It has been integrated to the equivalence checker.
For acceptance, the correctness of the tool is checked by comparing its output with the output of Design Compiler, using the equivalence checker, on about 24 VHDL and 10 Verilog real designs.
2. Pin Assignment Tool.
It is automatic package pin assignment tool. Along with automatic pin assignment, it allows manual changes. The user of the tool is ASIC Front end people.
The tool automatically does the placement of die Pad and package Ball. It has a user GUI interface. User can view Pad and Ball mapping, power rings, bonding pad and routing display. It has two views to show pad and ball connectivity.
3. Hardware Accelerator
The tool is a hardware accelerator. It claims 100X faster than software simulator. My task was to resolving hierarchical reference from the RTL code, it was involve writing of PLIs. Mapping RTL memory to hardware memory, It required understanding of hardware memory model. Merging waveform generated software simulator and hardware accelerator in fsdb, vcd, and WLF format.
4. FPGA Design
I was involved in the design, development and verification of FPGA. Target FPGA is vitex2Pro. I am responsible in design, development and verification of Decompression module.
5. Electrical Rule Checker
Electrical rule checking on spice netlist generated from DFII database.