Suman Chatterjee

Senior Software Engineer

Bengaluru, Karnataka, India26 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Clock-tree synthesis and optimization techniques.
Proven experience in HDL parsing and simulator integration.
Strong background in developing advanced semiconductor solutions.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in HDL parsing and optimization.

Contact

Skills

Core Skills

Clock-tree SynthesisOptimizationMulti-bit TechnologyRelative PlacementHdl ParsingSimulator Integration

Other Skills

CTSOptimization techniquesVHDL parserHDL simulator integrationVHDL-AMS supportVerilog parserData StructuresAlgorithmsC++

About

I am currently working at Synopsys (India) Private Limited. I am involved in developing Clock-tree- synthesis (CTS) solution. Previously I Architected the Physically aware Multi-bit flops banking solutions and developed Relative Placement (RP) technology. Prior to joining Synopsys, I worked in Interra Systems and Delsoft where I worked on various HDL parser and integrating them to HDL-simulator. I have received BE degree in Electrical Engineering from Jadavpur University in 1999. Specialties : C, C++, Algorithms and Data Structures.

Experience

26 yrs 11 mos

Total Experience

8 yrs 11 mos

Average Tenure

23 yrs 8 mos

Current Experience

Synopsys

Senior Staff R&D Engineer

Oct 2002 – Present · 23 yrs 8 mos · Bangalore

CTS/MSCTS engine for ICC2, FC
Multi-bit technology in ICC & ICC2, FC
Relative-Placement Technology in DC, ICC, ICC2, FC
Optimization techniques in ICC.

CTSMulti-bit technologyRelative PlacementOptimization techniquesClock-tree synthesisOptimization

Interra systems

Senior Software Engineer

Apr 2001 – Oct 2002 · 1 yr 6 mos · Kolkata

Jaguar, VHDL parser integration to Viewlogic Speedwave simulator
VHDL-AMS support to Jaguar and Speedwave simulator
Cheetah (Verilog parser) based VCS replacement Verilog simulator for Speedwave mixed kernel simulator
Vera parser development from scratch

VHDL parserHDL simulator integrationVHDL-AMS supportVerilog parserHDL parsingSimulator integration