Jul 2011 – Feb 2013 · 1 yr 7 mos

• Responsible for SoC design in the mobile application processor area.

Jan 2010 – Jun 2011 · 1 yr 5 mos

• SoC Design Manager , OMAP BU

May 2006 – Dec 2009 · 3 yrs 7 mos

• Responsible for Design-For-Test ( DFT) function - execution, planning, deliverables for a business unit out of TI India.

Jan 2005 – May 2006 · 1 yr 4 mos

• Managing a front end ASIC design group responsible for synthesis, Timing and DFT (Design for Test).

Nov 2000 – Jan 2005 · 4 yrs 2 mos

• Worked in multiple areas of hardware ASIC chip development including synthesis, STA with core specialization in the area of Design-For-Test (DFT). Design lead for a major 90nm networking chip with responsibility for planning, execution including DFT. Also worked in the areas of IP management ( libraries etc), Yield analysis. Working knowledge of various ASIC flows from TI, IBM,Agilent, TSMC. Played a part in setting up complete Customer-Owned ASIC flow ( COT) for the company.

Feb 1998 – Nov 2000 · 2 yrs 9 mos

• Worked in the areas of PCB design ( concept,planning,design,validation and ramp). Also worked on ASIC chip verification for 180nm mega modules.