SUNIL REDDY TETALA — Software Engineer

* Results-Driven Physical Design Engineer with over 3 years of experience and 4 successful tape outs of high frequency ( 400 to 1190 MHz ) blocks across advanced deep sub-micron nodes (3nm, 4nm and 6nm). Proven track record in delivering complex SoC designs for high-performance applications including WiFi 7, Metaverse VR Headset, Smartphone and Car Cockpit Display. * Expert in block-level implementation specializing in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, ECO, Sign-off, Timing Closure (STA), Physical Verification (PV) and Tapeout (GDSII). Adept at driving QoR and PPA improvements, resolving LEC, CLP, DRV, ERC, LVS, ANT ,EM, IR and SI issues in multi-voltage domain designs. * Skilled in building robust automation frameworks using Python, Tcl, Shell, and Makefile to accelerate design processes and improve workflow efficiency. * Passionate about developing scalable solutions, collaborating cross-functionally, and driving innovation in cutting-edge semiconductor technologies. * Key Skills & Tools :- Physical Design Tools: Cadence Innovus, Synopsys Fusion Compiler (FC), Synopsys ICC2, Synopsys PrimeTime (PT), Tweaker, Calibre, Xilinx Vivado Scripting Languages: Tcl, Python, Makefile Technology Nodes: 3nm, 4nm, 6nm

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in automation and high-frequency design.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 11 mos