Suyog Jagtap

Software Engineer

Bengaluru, Karnataka, India14 yrs 8 mos experience
Highly Stable

Key Highlights

  • 12+ years in Post Silicon IP Validation
  • Multiple technical awards for emulation Debug
  • Expertise in DFD Emulation and validation
Stackforce AI infers this person is a Semiconductor Validation Engineer with extensive experience in DFD Emulation and Post Silicon IP Validation.

Contact

LinkedIn

Skills

Core Skills

Post Silicon Ip ValidationDfd Emulation

Other Skills

DebuggingPowerOnTest Plan CreationVerilogAssembly LanguageTCL ScriptingPerlIEEE1588 protocolI2CCMOS LogicSolid State DevicesDigital Circuit DesignFPGACadence SpectreXilinx ISE

About

Emulation DFD Lead with 12+ years of experience at Intel/LSI/Tejas Networks in Post Silicon IP Validation and DFD Zebu Emulation. Worked on DFD Emulation for the Scalable Compute Product Group at Intel. Received multiple technical awards for emulation Debug, PowerOn, Completing key DFD flows as part FreezeGate Milestone and uncovering multiple RTL and FW bugs and Division recognition award for IP volume validation in Post Silicon.

Experience

14 yrs 8 mos
Total Experience
4 yrs
Average Tenure
2 yrs 7 mos
Current Experience

Amd

Senior Member of Technical Staff

Oct 2023 – Present · 2 yrs 7 mos

Intel corporation

Lead Design Engineer

Nov 2014 – Sep 2023 · 8 yrs 10 mos · Bengaluru, Karnataka, India

Post Silicon IP ValidationDFD EmulationDebuggingPowerOnTest Plan CreationVerilog+19

Lsi, an avago technologies company

R & D IC Design Engineer 2

Nov 2012 – Nov 2014 · 2 yrs · Pune

Tejas networks

R & D Engineer

Aug 2011 – Nov 2012 · 1 yr 3 mos · Bangalore

Education

Indian Institute of Technology, Guwahati

Master of Technology (M.Tech.) — VLSI

Jan 2009 – Jan 2011