Venkateswarlu Nagineni — Product Engineer
# Physical Design Engineer with 11+ years of Experience in Physical Design, Layout and Mixed Signal Designs. Expertise: Synthesis, Floor Planning, Placement, CTS, Congestion analysis, Routing, Static Timing Analysis and Closure, LEC, IR-Drop, EM and SI Analysis, Physical Verification (DRC/LVS/ERC) and Low power analysis..
Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in backend engineering and physical design.
Location: Hyderabad, Telangana, India
Experience: 12 yrs 1 mo
Career Highlights
- Over 11 years of experience in Physical Design Engineering.
- Expertise in Static Timing Analysis and Physical Verification.
- Proficient in multiple VLSI design tools and methodologies.
Work Experience
Intel Corporation
Physical Design Engineer (1 yr 11 mos)
SoC Design Engineer (3 yrs 9 mos)
Capgemini Engineering
Senior Professional 1 (2 yrs 5 mos)
Capgemini Engineering
Senior Engineer (1 yr 11 mos)
xSi Semiconductors Pvt Ltd
Design Engineer (2 yrs 1 mo)
RV-VLSI Design Center
ASIC Design Engineer Trainee (8 mos)
Education
Bachelor of Technology (B.Tech) at Princeton group of institutions
