Vijayalaxmi Raddiyavar — Product Engineer
PDK & SRAM Library Validation Engineer at Intel, specializing in comprehensive PDK validation and verification flows. 🔧 PDK Validation Expertise: DRC (Design Rule Check) — Calibre, Pegasus, ICV LVS (Layout Versus Schematic) — Calibre, Pegasus, ICV PEX (Parasitic Extraction) — Calibre xRC, StarRC ERC (Electrical Rule Check): Antenna Rule Check Validation. Design Rule Manual (DRM) Verification PCELL Validation & Testing SPICE Model Validation Layer Map & Display File Verification 🔧 SRAM & Library Validation: SRAM Library Validation & Characterization Standard Cell Library Validation Liberty File (.lib) Validation LEF/DEF Validation Pre & Post Layout Simulation. Layout vs Schematic Verification 🛠️ Tools & Technologies: Cadence Virtuoso, Spectre Calibre — DRC/LVS/PEX Synopsys StarRC HSPICE, Spectre Python Scripting & Automation Tcl/SKILL Scripting
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in PDK and SRAM processes.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 6 mos
Skills
- Sram
- Library Validation
- Component Design
- Pdk Validation
- Simulation
Career Highlights
- Expert in PDK and SRAM validation processes.
- Proficient in automation and validation of semiconductor designs.
- Strong background in VLSI circuit design and testing.
Work Experience
Intel
SRAM library validation (2 yrs 6 mos)
Component Design Engineer (2 yrs 8 mos)
PDK library validation (1 yr 1 mo)
TNP CELL NIT GOA
Training and placement coordinator (1 yr 7 mos)
Education
Master of Technology - MTech at National Institute of Technology, Goa
High School Diploma at Jawahar Navodaya Vidyalaya - JNV
Bachelor of Engineering - BE at Basaveshwar Engineering College (A), Bagalkote
XI-XII at KLESs J.T.college of Arts, Science & Commerce Gadag.
MA psychology at Indira Gandhi National Open University
