Vipin Varghese — CEO

I build userspace dataplanes (DPDK/eBPF/XDP) for proxies, IDS/IPS, capture & L7 services. Recent wins: p99 ↓45% and 60 Gbps @ fewer cores on AMD EPYC Turin Dense via CCD-aligned pinning, IRQ/RSS affinity, and THP tuning. I speak at DPDK Summits and intial contributor packet-processing code paths (Suricata/DPDK). Topics I love: NUMA/NPS trade-offs, uncore/L3 alignment in K8s, TCP/QUIC offloads, flamegraphs. Speaker: DPDK Summit APAC & Montreal 2024. Repos & talks in Featured. Diversified experience in Network Application Acceleration with a focus on analysis, performance tuning, and architecting solutions using technologies such as DPDK (x86), Ezchip (NP4, NP5), Tilera (8036, 8072) on Linux for user and kernel. Keen interest in building solutions using Heterogeneous cores for accelerating applications like security, network monitoring, and crypto (IPSEC and TLS). - high throughput (10G, 25G, 40G) for Suricata IDS/IPS acceleration - Transparent SSL-TCP proxy - WAN Accelerator, dynamic Load distributor using IP, GRE, GTP, TLD Sessions. Key Areas: - Tilera mTCP & matrixssl on gx8036 & gx8072, use of OpenSSL library for dynamic certificate generation for proxy SSL. - NPU: Ezchip NP4 & NP5: Microcode, Driver & SDK for OpenFlow 1.3 agent. - DPDK: Accelerating & Porting IDS/IPS on DPDK, Virtual Switch-Router, Multi-Process work distributor, debug and tools for memory & process space corruption analysis, TUN library, performance and functional tuning. - XDP: pinning of flows to worker and inspection of meta-data for HW offload. - TCP: data acceleration via compression & decompression via SW and HW FPGA https://github.com/vipinpv85/

Stackforce AI infers this person is a Networking Engineer specializing in Data Plane Development and Performance Optimization.

Location: Bengaluru, Karnataka, India

Experience: 18 yrs 5 mos

Skills

Data Plane Development Kit (dpdk)
Linux
C

Career Highlights

Achieved 90Gbps performance improvement in NETMAP IPSEC.
Enhanced DPDK performance tuning for AMD EPYC.
Speaker at DPDK Summits sharing expertise.

Work Experience

AMD

Principal Member of Technical Staff (1 yr 10 mos)

Senior Member of Technical Staff (4 yrs 3 mos)

Intel Corporation

Network Software Engineer (3 yrs 4 mos)

Software Development Engineer (2 mos)

Application Engineer (2 yrs 3 mos)

Accel Frontline Ltd

Technical Lead (1 yr 7 mos)

Radisys Corporation

Senior Software Engineer (1 yr 5 mos)

Altior Inc.

Software Engineer (1 yr)

Movik Networks

Software Engineer (10 mos)

OpenClovis

Software Engineer (11 mos)

L&T Infotech

Software Engineer (2 yrs 10 mos)

Education

B.tech at Sahrdaya College of Engineering & Technology

Vipin Varghese

CEO

Bengaluru, Karnataka, India18 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Achieved 90Gbps performance improvement in NETMAP IPSEC.
Enhanced DPDK performance tuning for AMD EPYC.
Speaker at DPDK Summits sharing expertise.

Stackforce AI infers this person is a Networking Engineer specializing in Data Plane Development and Performance Optimization.

Contact

Skills

Core Skills

Data Plane Development Kit (dpdk)LinuxC

Other Skills

perfDPDKC (Programming Language)Python (Programming Language)DebuggingDistributed SystemsProgrammingTCP/IPMultithreadingHigh AvailabilitySoCInternet Protocol Suite (TCP/IP)MicrocontrollersSoftware DesignEthernet

About

Experience

18 yrs 5 mos

Total Experience

2 yrs 3 mos

Average Tenure

4 yrs 3 mos

Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

Jul 2024 – Present · 1 yr 10 mos

Identfied the cause of latency on Intel E830 for both Linux and DPDK driver.
Root cause and resolve VHOST DPU driver overhead at PCIe level.
Helped streaming & hosting customer to improve NETMAP IPSEC from 18Gbps to 90Gbps, CPU threads reduced from 28 to 12 (both Control Plane and Data Plane).
QDMA Poll Mode Driver enhancement towards AVX512 SIMD.
QDMA Poll Mode driver development on ARM Ampere using NEON, achieving 55% reduction in RX-TX (almost 2.8us) for API latency and double the packets per second over scalar code.
ARM Ampere NEON based DMA and BBDEV PMD development and performance enhancement achieving 45% reduction on latency vs scalar and uplift from 14Gbps to 25Gbps.

CLinuxperfData Plane Development Kit (DPDK)

Senior Member of Technical Staff

Feb 2022 – Present · 4 yrs 3 mos

1. Enhanced IPSEC-MB (IPSEC crypto and SHA) for AMD EPYC MILAN (no-avx512) to meet 85% of the Competitive Platform with AVX512.
2. Enabled Open Air Interface (OAI) to use DPDK bbdev and Crypto offloads for HW acceleration.
3. Reworked QDMA Poll Mode Driver to achieve 200Gbps for payload sizes from 256 Onward, achieving 205Mpps with 64B.
4. Enhanced DPDK SW DMA to deliver 3x Mpps per core on AMD EPYC Milan|Genoa|Siena.
5. We enhanced the Baseband Poll Mode Driver to achieve 500us to 20us for encoding and decoding for SD-FEC FPGA IP.
6. Tuning guide for DPDK for Milan and Genoa, identifying BIOS and Kernel settings for DPDK, VPP, OVS for AMD EPYC SoC.
7. Identified Data path performance issues for 5G UPF and optimized for AMD EPYC for telecom customers.
8. Worked on cache-to-cache latency, core-to-core latency, Simple Non-Temporal stores for Burst requests, and workarounds for per-core boost support on ROME & MILAN.
9. Evaluate and analyze competitive DMA engines for power, throughput, latency, memory bandwidth, QoS and transparent DMA engine offload cases.
10. Performance tuning and optimization on split LLC compute complexes
11. Introduce LLC load-aware data spread across tiles (individual L3) to achieve higher Mpps and lower latency.
12. Baseline & apply AMD EPYC Smart Data Cache Injection into DPI and UPF workload.
patches:
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/653120.html
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1e3aa9c9278db69d4bdb661a750a7268789188d6

C (Programming Language)Data Plane Development Kit (DPDK)Python (Programming Language)C

Intel corporation

3 roles

Network Software Engineer

Promoted

Sep 2018 – Jan 2022 · 3 yrs 4 mos

Path Finding: Prototype and optimize
1. Katran L4 load balancer to offload from Server Processor to SmartNic, Appliance Card, and IPU with the help of GRPC and EBPF MAP.
2. Centralized video and sensory data from Vehicle, allowing zero-copy to opencv for object identification on the received data and update to AWS gateway using SoC.
3. Video/Audio Streaming libraries compliant to ST 2110 on COTS and Foundational NIC using Linux DPDK and Windows DPDK.
4. Identified shortcomings in Windows DPDK compared to Linux DPDK, provided workarounds, and patches to fix the issues.
5. IA cores on PCIe card for Hardware & Software Acceleration with DPDK and XDP eBPF.
Accelerated on IA cores and NIC for multi-tenant open VPN.
6. REST/GRPC converged data plane for Hardware offload at edge and Cloud solutions for computing, storage, and AI.
7. AF_XDP PMD with external mbuf.
8. Wired and Wireless NIC PMD to access millimetre-wave via openwrt, DPDK and VPP.
9. Next-Gen Firewall IDS-IPS on HW accelerated SoC.
10. QUIC Proxy acceleration on Host and Smart NIC CPU.
11. Frugal 5G: Arduino Microcontroller program for System management (Power-on, RST, Serial Comm, Interrupt-driven event).
DevConf 2019: How to debug application applications in DPDK
Patent: Pending US20220201061A1

Software Development Engineer

Jan 2018 – Mar 2018 · 2 mos

1. Work and collaborate with DPDK team.
2. Design and integrate TUN PMD.
3. Bug fixes and performance optimization for Software scheduler of Eventdev and compression library.

Application Engineer

May 2016 – Aug 2018 · 2 yrs 3 mos

a. Config fetch &suggest for best configuration on host & guest built on KVM-QEMU.
b. Prototype use cases leveraging virtio, tap, tun on host and Guest with OVS and DPDK solution for telecom.
c. pre-5G interface environment coding and setup
d. Performance tuning, bug fixes and documentation updates to DPDK mainline.
e. Prototype, Bug fix and built POC on SoC for telecom solutions with DPDK acceleration.
Terragraph:
a. Setup and modify code base for DPDK and VPP to run on openwrt 32 bit.
b. Optimize SGMII PMD and radio PMD for saving cycles and using SIMD LD,STR,CMP
Frugal 5G:
a. Adriuno Microcontroller program for System management (Power-on, RST, Serial Comm, Interupt driven event)
b. Python Host for Edison for managing System
c. Code review and optimization for PIC microcontroller for RF module
https://mail.openvswitch.org/pipermail/ovs-dev/2017-June/333760.html
Conference:
Speaker DPDK 2018 BLR, India Summit - https://dpdkbangalore2018.sched.com/event/Dr5d/memzone-monitor
Speaker Packet builder NFV JUL 2018, THREAD-STACK-REGISTER for data & control threads in DPDK.

Accel frontline ltd

Technical Lead

Sep 2014 – Apr 2016 · 1 yr 7 mos · Cochin Area, India

Designed and Developed from the ground up for 40Gb SSL proxy with mtcp and matrixssl.
Fast path library for certificate generation with caching and IP white list.
DPDK acceleration open IDS|IPS solution for 68% performance on 60 bytes frames on x86_64 platform.
Tilera Virtual NIC DPDK Poll Mode Driver. Prototype user space PMD over user-pcie-rings for fast path threat analyzer on Tilera Platform.
Transparent WAN Control plane offloading features of ARP, ICMP, Route, LLDP, Load Balancer for VM using DPDK.
Stateless Packet generator for 40G GTP using DPDK.
Hyperscan assist DPDK Suricata for NFV and threat analyzer.
Proof of Concept: 80G GTP traffic filter and IDS using DPDK.

Radisys corporation

Senior Software Engineer

Mar 2013 – Aug 2014 · 1 yr 5 mos · Bengaluru Area, India

Designed & Developed Network Flow Engine for 100G network switch.
Ported & Enhanced EZchip SDK driver to support for Dual NPU.
Diagnostic tool for EZchip NPU to debug at the engine and low level.
Keep alive heartbeat interconnecting NPU.
Suggested DPDK for Platform Service and HA between blades and workload distribution.
Mentored and guided interns & helped new team members in getting acquainted with the product, functionality & features translated to NPU based OF 1.3.1.
Built NPU (Microcode) functionality based Open Flow 1.3.1 for Flow ACL (Non-IP, IPV4 & IPV6, Protocols like NvGRE, GTP), Dynamic Hash and token-based Load balancing, Flow classification & learning for data plane services, Work distributor to multi-blade array running DPDK accelerated applications, Policed Packet Into Open Flow controller, Drop, Port Forward, Goto features for ACL, FIB, LB for state-full/less, Protocol aware Forwarding & Hash/Round Robin based Packet Distribution for inner & outer IP layer.

Altior inc.

Software Engineer

Mar 2012 – Mar 2013 · 1 yr · Bengaluru Area, India

Prototype & demo transparent TCP interception in Linux for SSL & WAN. Offloaded the acceleration using Software and Hardware FPGA.
Implemented search & lookup (fast tree) for IP-Port matching.
Brainstormed & suggested approaches for inline FPGA routines for Packet Identification, header parsing.
Took initiative & worked on SW based transparent compression & decompression with Fast Port Lookup.
Suggested & prototype work distribution to multi-queue on Kernel to FPGA.

Movik networks

Software Engineer

May 2011 – Mar 2012 · 10 mos · Bengaluru Area, India

Platform and availability for Line cards & applications.
Open IPMI interface for node-aware applications.
ATCA Interface for HW and SW to System Integration Test for Availability, Software Upgrade, Data Path & Network Statistics for RAN Aware via automation.
Reduced network statistics profiler from 380% to 84% CPU & 83% in total time via distribution & hash look-up processing.
Enhanced Network Monitor Element for PCRF (Policy Charging & rules Function) & updates.

Openclovis

Software Engineer

May 2010 – Apr 2011 · 11 mos · Bengaluru Area, India

Tweaked cluster membership & leader election in Cluster nodes.
Enhanced group membership (blade/node independent application failover).
Configuration & Management for HA on non-SAF nodes & interfaced to EPON Link Aggregation Module for Telecom Malaysia.
Improved Director & Test Automation Environment for supporting SAF & non-SAF applications.

L&t infotech

Software Engineer

Jul 2007 – May 2010 · 2 yrs 10 mos · Navi Mumbai, Chennai, India

Network Interface Switching Unit for Postdata South Korea Wimax RNC:
Kernel & OAM for the Line card in RAS (Radio Access System).
Tunnel Transport Layer Security Integration for Authentication & data path encryption for UE (User Equipment) connected to AAA.
Message Manager, Statistics & report generator for job scheduling on simulated ACR and EMS with SNMP for Wimax message replay for RAS, ACR & EMS.
Automation framework & tools for validating EMS (Element Management System) functional, performance & load.
Multi-core Power PC Freescale pre-silicon validation with LINUX BSP: Automation Framework, test suites & Scenarios for Linux BSP & IDE releases for FSL SoC. Use cases as PoC for packet steering, L2/L3/L4 hash tuple.