VISHAL SAHA — Software Engineer

Prime Closure: Automated timing analysis and Reporting in prime closure using Python Performed ECO fixes to address timing violations during post route signoff . Performed detailed setup , hold to ensure timing integrity at signoff . PRS Flow : Implemented PRS improve the quality of results (QoR) and reduce design closure iterations. Executed PRS flow to optimize design timing and area at the pre-physical stage, ensuring better predictability in the backend. Experienced in Microsoft co-pilot ETM (Encounter Timing Model): Developed and implemented Encounter Timing Models (ETM) to optimize timing analysis for signoff. Integrated ETM with PrimeTime for enhanced timing accuracy in large-scale digital designs. Supported the generation and validation of timing models for use in timing closure.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in timing analysis and debugging.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 8 mos