Sep 2021 – Present · 4 yrs 8 mos

• Led the backend development of all Super Compute SoCs (GPUs) at Intel through the complete development cycle. Responsible for the overall SD development for the multiple product lines in market-winning tactical and strategic products.
• Personally led/managed the most complex SoC (GPU) for Data Center & High Performance Computing, Machine Learning and inference servers – a multi-die solution with advanced industry process technologies, interconnect technologies, packaging technologies, and novel design methodologies while interacting with all the major stakeholders like arch, rtl, val, DA and EDA vendors.

Jun 2017 – Present · 8 yrs 11 mos

• Led the most complex chips on Structural domain which included the first 3D chip and the biggest chip. Perssnally let the Arch changes needed for the design closure, interface spec closure for IPs and defining the convergence criterias along with driving the complete chips from RTL to Tape-in.
• Technically led more than 100 member teams while working on the projects

May 2014 – Oct 2021 · 7 yrs 5 mos

• Led the power delivery arch and implementation on the integrated GFX IP. Owned the methodology, flows and implementation of power delivery, reliability verificaiton and load line.
• Led more than 5 programs with a team of more than 25 members owning from planning to tapein of the power delivery and reliability and verification.
• Defined, designed and coded the flows which were used acrossed all the projects with multiple vaiables controled by project owners centrally to make the flow very flexible across projects and very controlled within a project

Dec 2009 – Apr 2014 · 4 yrs 4 mos

• Led the section level closure for Integrated graphics with a team of 10 members. As Section lead, was reponsible for the section closure on all the design vectors while improving the utilization more than 7% over earlier projects and closure of the design more than 2 quarterd in advance. Increased the tech competence of team on STA, FV, PDN and APR over the design cycle.
• Was key member in increasing the team strength by more than 2X over the duration of 4 yrs.

Mar 2006 – Nov 2009 · 3 yrs 8 mos

• Owned set of blocks for closing the same across all the design vectors.
• Owned the ECO flows for all the blocks as part of the team and led all the timing and functional ECOs for more than 10 partitions as part of the process owner reponsibility.

May 2003 – Apr 2006 · 2 yrs 11 mos

• Responsible for validating EDA tools and evolving enviornment for using those tools to make the most of tools for different design teams across company.
• Owned the DRC, density and Antenna flows for complete Intel Communications Group and improved the runtimes of the density and Antenna by more than 2X during the tensure.