Apr 2021 – Jul 2025 · 4 yrs 3 mos · Sunnyvale, California, United States

• Our team has built and maintains Target's GPU cluster for training and inference. This includes a petabyte scale high-performance cache for the cluster with 400% higher throughput than the incumbent solution.

Jun 2019 – Mar 2021 · 1 yr 9 mos

• Post-silicon workload analysis and performance tuning
• Decode unit verification team site lead for AMD's next generation x86 CPU core

Oct 2014 – Jun 2019 · 4 yrs 8 mos

• Developed a new performance optimization methodology to identify workload specific CPU configuration for a Zen core based client SoC
• Received AMD's VP Spotlight award, which is awarded to engineers in recognition of their outstanding performance

Jun 2013 – Sep 2014 · 1 yr 3 mos

• I was an intern on AMD's CPU core verification team. I chose to work on improving the quality of constrained random test programs.
• I analysed the performance of the various in-house x86 random assembly-test generators using functional coverage as a metric. To fill in the coverage gaps of stimulus generators, I developed a test filtering methodology which can identify functional tests capable of achieving desired coverage prior to RTL simulation. This methodology is test generation program agnostic and can be used to achieved desired coverage results with up to 900x lesser test volume.

Apr 2016 – Oct 2016 · 6 mos · Austin, Texas Area

• As a part of AMD's FastForward 2 research, I worked on a high-level architecture simulator. I used a neural-net based model to estimate the power and performance of next generation GPUs across various hardware configurations and benchmarks.

Sep 2012 – Jun 2013 · 9 mos · Santa Barbara County, California, United States

• I continued researching the relationship between randomly generated assembly tests and architectural machine states known to trigger interesting events. By learning the relationship of specific microarchitectural events with architectural state values, their occurrence can be predicted using high-level simulation results.

Sep 2011 – Jun 2012 · 9 mos · Santa Barbara County, California, United States

• Explored the possibility of predicting behaviors observed in a low level description of a design (say gate-level netlist) based on the design's high level description (such as RTL).
• Based on studies performed on an OpenSPARCH T2 microprocessor, demonstrated that assembly tests that generate peak power conditions (measured using PT-PX from RTL simulations) can be predicted from architectural simulations. See my paper from ITC 2012.

Sep 2010 – Jun 2011 · 9 mos

• Working on test content optimization for post-silicon performance validation and RTL verification using data learning algorithms under Li-C Wang.

Jun 2012 – Sep 2012 · 3 mos · Hillsboro

• I worked with the Strategic CAD Labs(SCL) at Intel.
• I was able to demonstrate that PCIe high volume EV margins can be predicted using sort and register readout values by means of a 25-fold cross validation of a tree-based rule learning model.
• EV volume testing for PCIe involves margining at nominal conditions to pick ~10 representative parts (from a lot of ~100 parts) to be subjected to DoE across various P,V,T, Z corners. Determining PCIe loopback tests’ eye-diagram margins is a time-intensive process. Predicting these margins using sort and/or class data to identify best and worst case dies can greatly reduce test time spent on picking parts for DoE tests.
• The goal of the internship was to build models using sort and register readout values to predict the margins without having to actually run the tests. The flow used tree-based rule learning to build a prediction model. It was implemented using Rapidminer (an open source data exploration tool).

Jun 2011 – Sep 2011 · 3 mos · Santa Clara

• I worked with the SPARC M4 processor post-silicon validation team.
• I was in charge of wafer test and final test data analysis. I helped develop infrastructure to monitor incoming silicon data on a daily basis and identify process shifts or abnormalities.

Jun 2008 – Aug 2010 · 2 yrs 2 mos

• Now owned by Avago, LSI was a leading provider of innovative silicon, systems and software technologies including custom and standard product ICs, adapters, systems and software.
• In my role as a front-end design engineer, I owned the formal verification based RTL vs gate-level netlist logical equivalence checks and test-mode STA of a 40nm SSD controller SoC.
• I was also involved in the functional verification of a 65nm hard-disk read channel using Verilog and SV test bench environments.

Jun 2007 – Jul 2007 · 1 mo

• Ittiam Systems is an Embedded Software and Systems Design Company which specializes in Digital Signal Processing (DSP) based applications in Multimedia and Communications domains. Its core competencies include RTL Design, Multimedia Codec, Middleware, Board Design and Application Software.
• As a summer intern, I implemented the Real-time Protocol(RTP) header format for MPEG4 Elementary Streams (RFC3640).

Jun 2006 – Jul 2006 · 1 mo · Mumbai Metropolitan Region

• SAMEER is a premier R & D Laboratory dedicated to research, design and development in the field of RF and Microwave systems. The headquarters of SAMEER is located on the campus of IIT Powai in Mumbai
• As a summer intern, I designed and implemented a micro-controller driven dot-matrix display with optical shaft encoder input for use in high temperature electrical furnaces