Pravin Bagul

Software Engineer

Pune, Maharashtra, India8 yrs 5 mos experience

Highly Stable

Key Highlights

Over 6 years of experience in VLSI domain.
Expertise in RTL Design and ASIC Design.
Proven track record in developing advanced computing systems.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and RTL design.

Contact

Skills

Core Skills

Asic DesignRtl DesignCdcLint

Other Skills

DveVerdiLogic SynthesisRTL DevelopmentVerilogStatic Timing AnalysisApplication-Specific Integrated Circuits (ASIC)QuestasimVivadoSystemVerilogSystemCTiming ClosureCPU designMicroarchitecture

About

A young and dynamic professional with more than 6 years of experience in the VLSI domain with exceptional skills in RTL Design, Lint and CDC check, looking for a challenging role in organisation pushing the frontiers of next-generation technology.

Experience

Synopsys inc

Senior Staff Engineer

Aug 2024 – Present · 1 yr 7 mos · Pune, Maharashtra, India · Hybrid

D2D UCIE Design

DveVerdiLogic SynthesisAsic designRTL DesignRTL Development+13

Qualcomm

2 roles

Senior Lead Engineer

Nov 2022 – Jul 2024 · 1 yr 8 mos · Bengaluru, Karnataka, India

CDCLint

Senior Design Engineer

May 2020 – Nov 2022 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Centre for development of advanced computing

Knowledge Associate

Sep 2017 – May 2020 · 2 yrs 8 mos · Pune Area, India

Part of a team working on developing Network Interface cards (NIC) for enhancing network speed of India’s indigenous “Trinetra” Series of high computing systems.